Method and apparatus for efficiently managing architectural register state of a processor

Patent metadata

Field	Value
Publication number	US-9804842-B2
Application number	US-201414581535-A
Country	US
Kind code	B2
Filing date	Dec 23, 2014
Priority date	Dec 23, 2014
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

An apparatus and method for efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: a source mask register to be logically subdivided into at least a first portion to store a usable portion of a mask value and a second portion to store an indication of whether the usable portion of the mask value has been updated; a control register to store an unusable portion of the mask value; architectural state management logic to read the indication to determine whether the mask value has been updated prior to performing a store operation, wherein if the mask value has been updated, then the architectural state management logic is to read the usable portion of the mask value from the first portion of the source mask register and zero out bits of the unusable portion of the mask value to generate a final mask value to be saved to memory, and wherein if the mask value has not been updated, then the architectural state management logic is to concatenate the usable portion of the mask value with the unusable portion of the mask value read from the control register to generate a final mask value to be saved to memory.

First claim

What is claimed is:

1. A processor comprising:
a source mask register to contain a mask logically subdivided into at least a first portion to store a usable portion of a mask value and a second portion to store an indication of whether the usable portion of the mask value has been updated, wherein the usable portion is designed to be used for one or more mask operations;
a control register, separate from the source mask register, to store an unusable portion of the mask value; and
architectural state management logic to read the indication to determine whether the mask value has been updated prior to performing a store operation, wherein if the mask value has been updated, then the architectural state management logic is to read the usable portion of the mask value from the first portion of the source mask register and zero out bits of the unusable portion of the mask value to generate a final mask value to be saved to memory, and wherein if the mask value has not been updated, then the architectural state management logic is to concatenate the usable portion of the mask value with the unusable portion of the mask value read from the control register to generate a final mask value to be saved to memory.

2. The processor as in claim 1 wherein the source mask register comprises a 64-bit register and wherein the usable portion of the mask value comprises a 16-bit value.

3. The processor as in claim 2 wherein the indication comprises a 1-bit value to indicate with a first value that the usable portion of the mask has been updated and to indicate with a second value that the usable portion of the mask has not been updated.

4. The processor as in claim 2 wherein the unusable portion of the mask value comprises bits [ 63 : 16 ] and the usable portion of the mask value comprises bits [ 15 : 0 ].

5. The processor as in claim 1 further comprising a control register bus interface communicatively coupling the control register to the architectural state management logic.

6. The processor as in claim 1 wherein the architectural state management logic is to execute a plurality of micro-operations to perform the operations of reading the indication and the usable portion of the mask value, generating the final mask value, and saving the final mask value to memory.

7. The processor as in claim 1 wherein the architectural state management logic is to perform a restore operation by reading a mask value from memory, storing the unusable portion of the mask value in a control register and storing the usable portion of the mask value in the source mask register.

8. The processor as in claim 7 wherein the architectural state management logic is to initially set the indication to indicate that the usable portion of the mask value has not been updated.

9. The processor as in claim 8 wherein the usable portion of the mask value is to be stored in bits [ 15 : 0 ] of the source mask register and the indication is to be stored in bit [ 16 ] of the source mask register.

10. The processor as in claim 9 further comprising:
a general-purpose register (GPR), wherein the architectural state management logic is to initially store the mask value in the GPR from which it will then copy the unusable portion to the control register and copy the usable portion to the source mask register.

11. A method comprising:
storing a usable portion of a mask value of a mask in a source mask register having a storage capacity greater than the usable portion of the mask value, wherein the usable portion is designated to be used for one or more mask operations;
storing in the source mask register an indication as to whether the usable portion of the mask value has been updated;
storing an unusable portion of the mask value in a control register separated from the source mask register; and
reading the indication to determine whether the mask value has been updated prior to performing a store operation, wherein if the mask value has been updated, then reading the usable portion of the mask value from the source mask register and zeroing out bits of the unusable portion of the mask value to generate a final mask value to be saved to memory, and wherein if the mask value has not been updated, then concatenating the usable portion of the mask value with the unusable portion of the mask value read from the control register to generate a final mask value to be saved to memory.

12. The method as in claim 11 wherein the source mask register comprises a 64-bit register and wherein the usable portion of the mask value comprises a 16-bit value.

13. The method as in claim 12 wherein the indication comprises a 1-bit value to indicate with a first value that the usable portion of the mask has been updated and to indicate with a second value that the usable portion of the mask has not been updated.

14. The method as in claim 12 wherein the unusable portion of the mask value comprises bits [ 63 : 16 ] and the usable portion of the mask value comprises bits [ 15 : 0 ].

15. The method as in claim 11 wherein storing and reading from the control register is performed via a control register bus interface.

16. The method as in claim 11 further comprising executing a plurality of micro-operations to perform the operations of reading the indication and the usable portion of the mask value, generating the final mask value, and saving the final mask value to memory.

17. The method as in claim 11 wherein a restore operation is to be performed by reading a mask value from memory, storing the unusable portion of the mask value in a control register and storing the usable portion of the mask value in the source mask register.

18. The method as in claim 17 further comprising:
initially setting the indication to indicate that the usable portion of the mask value has not been updated.

19. The method as in claim 18 wherein the usable portion of the mask value is to be stored in bits [ 15 : 0 ] of the source mask register and the indication is to be stored in bit [ 16 ] of the source mask register.

20. The method as in claim 19 further comprising:
initially storing the mask value in a general-purpose register (GPR) from the unusable portion is copied to the control register and the usable portion is copied to the source mask register.

Assignees

• Intel Corp

Inventors

• Corbal San Adrian Jesus
• Bradford Dennis R
• Chaffin Benjamin C
• Bahrami Taraneh
• Hall Jonathan C
• Maciukenas Thomas B
• Gramunt Roger
• Sharma Rohan

Classifications

• G06F9/30072

  to perform conditional operations, e.g. using predicates or guards · CPC title

• G06F9/30032

  Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE · CPC title

• G06F9/30018

  Bit or string instructions · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F15/8084

  Special arrangements thereof, e.g. mask or switch · CPC title