Wearable device assembly with ability to mitigate data loss due to component failure

Patent metadata

Field	Value
Publication number	US-9804792-B2
Application number	US-201615084154-A
Country	US
Kind code	B2
Filing date	Mar 29, 2016
Priority date	Jun 12, 2013
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A wrist-worn device monitors movements of a user with a flexible circuit member. The flexible circuit member is fault tolerant. It may contain extra and/or redundant traces as well as the ability to store data on RAM if the flash memory fails or if some or all trace connections between the processor and flash memory fail. Data stored on the RAM may or may not contain less fidelity. Lower fidelity data may be used to alleviate issues arising if the RAM has less storage capacity than the flash memory.

First claim

What is claimed is:

1. A method comprising:
receiving, by a computing device, sensor data generated by a sensor, the sensor data indicating one or more sensed movements of a user;
identifying, by the computing device, whether a connection to a flash memory is available;
when the connection to the flash memory is available, sending the sensor data to the flash memory via a plurality of traces; and
when the connection to the flash memory is not available, storing the sensor data in a RAM of a processor of the computing device.

2. The method of claim 1 , wherein the processor is operatively connected to the sensor.

3. The method of claim 1 , wherein the storing the sensor data in the RAM of the processor further comprises:
storing sensor data in the RAM of the processor at a reduced fidelity.

4. The method of claim 3 , wherein the reduced fidelity is due to lower recordings per a given unit of time.

5. The method of claim 3 , wherein the reduced fidelity is due to storing the sensor data in a compressed format.

6. The method of claim 3 , wherein the reduced fidelity is due to storing predetermined types of data.

7. The method of claim 1 , further comprising:
determining, by the computing device, a break in a first trace of the plurality of traces; and
in response to the determining the break in the first trace, sending the sensor data to the flash memory via a first alternative trace.

8. The method of claim 1 , further comprising:
determining, by the computing device, a break in a first trace of the plurality of traces; and
determining, by the computing device, one or more alternative traces to accept the sensor data.

9. A method comprising:
receiving, by a computing device, sensor data generated by a sensor, the sensor data indicating a sensed movement of a user;
identifying, by the computing device, whether a flash memory fails;
when the flash memory has not failed, sending the sensor data to the flash memory; and
when the flash memory fails, storing the sensor data in a RAM of a processor of the computing device, wherein the processor is operatively connected to the sensor.

10. The method of claim 9 , further comprising:
determining, by the computing device, that the RAM is approaching a first low capacity threshold; and
in response to the determining that the RAM of the processor has reached the first low capacity threshold, operating the computing device in a first operational mode, wherein the sensor data is stored in the RAM of the processor at a reduced fidelity.

11. The method of claim 10 , wherein the reduced fidelity is due to lower recordings per a given unit of time.

12. The method of claim 10 , wherein the reduced fidelity is due to storing predetermined types of data.

13. The method of claim 10 , wherein the reduced fidelity is due to storing the sensor data in a compressed format.

14. The method of claim 10 , wherein the first low capacity threshold corresponds to a remaining memory capacity of the RAM of the processor.

15. The method of claim 10 , further comprising:
determining, by the computing device, that the RAM is approaching a second low capacity threshold; and
in response to the determining that the RAM of the processor has reached the second low capacity threshold, operating the computing device in a second operational mode, wherein the computing device is configured to cease one or more data recording functions performed by the computing device.

16. The method of claim 15 , wherein the second low capacity threshold is set at a level above the first low capacity threshold.

17. A method comprising:
receiving, by a computing device, sensor data generated by a sensor, the sensor data indicating a sensed movement of a user;
identifying, by the computing device, whether a trace connecting a processor of the computing device and a flash memory of the computing device fails;
when the trace connecting the processor and the flash memory does not fail, transmitting the sensor data from the processor to the flash memory with a first transmission scheme; and
when the trace connecting the processor and the flash memory does fail, transmitting the sensor data from the processor to the flash memory with a second transmission scheme different from the first transmission scheme, wherein the transmitting the sensor data uses a set of traces.

18. The method of claim 17 , wherein the second transmission scheme is a time division scheme.

19. The method of claim 17 , wherein the second transmission scheme is a statistical multiplexing scheme.

20. The method of claim 17 , further comprising:
determining, by the computing device a break in a first trace, of the set of traces; and
in response to the determining the break in the first trace, sending the sensor data to the flash memory via a first alternative trace, wherein the first alternative trace is included in the set of traces.

Assignees

• Nike Inc

Inventors

• Haensly Jason
• Lapinsky Mike
• Mckeag Greg
• Zipperer James

Classifications

• G06F11/3438

  monitoring of user actions (tracking the activity of the user H04L67/535) · CPC title

• G06F11/2097

  maintaining the standby controller/processing unit updated (initialisation or re-synchronisation thereof G06F11/1658 and subgroups) · CPC title

• G06F2212/7209

  Validity control, e.g. using flags, time stamps or sequence numbers · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title