Array substrate and manufacture method thereof

Patent metadata

Field	Value
Publication number	US-9804459-B2
Application number	US-201514424007-A
Country	US
Kind code	B2
Filing date	Feb 8, 2015
Priority date	Dec 1, 2014
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

The present invention provides an array substrate and a manufacture method thereof. The array substrate, by locating both a black matrix and a color resist layer on the array substrate, and locating the color resist layer on the TFT layer prevents the bad influence to the color resist layer from the high temperature TFT process, and accordingly to make the liquid crystal panel with higher display quality. The manufacture method of the array substrate, first forms a black matrix on the substrate, and second implements TFT manufacture process on the black matrix, and then forms a color resist layer after the TFT manufacture. Accordingly, both the black matrix and the color resist layer manufactured on the array substrate can be achieved, and with forming the color resist layer after the TFT manufacture to prevent the bad phenomenon due to bubbles generated by the color resist volatilization from the high temperature TFT process, and accordingly to effectively make the liquid crystal panel with higher display quality and raise production yield.

First claim

What is claimed is:

1. An array substrate, comprising a substrate, a black matrix located on the substrate, a TFT layer located on the black matrix, a color resist layer located on the TFT layer, a second passivation layer and a pixel electrode layer;
wherein the TFT layer comprises a source/a drain located on the black matrix, a semiconductor layer located on the source/the drain, a gate isolation layer located on the semiconductor layer, a gate located on the gate isolation layer and a first passivation layer located on the gate; and
wherein the color resist layer is arranged above and separated from the black matrix.

2. The array substrate according to claim 1 , wherein the color resist layer is located on the first passivation layer, the second passivation layer is located on the color resist layer, and the pixel electrode layer is located on the second passivation layer, and the array substrate further comprises a via hole penetrating the second passivation layer, the color resist layer, the first passivation layer, the gate isolation layer and the semiconductor layer, and the pixel electrode layer is electrically connected with the source/the drain by the via hole.

3. The array substrate according to claim 1 , wherein the pixel electrode layer comprises a first ITO electrode layer and a second ITO electrode layer, and the first ITO electrode layer is located on the first passivation layer, and the array substrate further comprises a via hole penetrating the first passivation layer, the gate isolation layer and the semiconductor layer, and the first ITO electrode layer is electrically connected with the source/the drain by the via hole, and the color resist layer is located on the first ITO electrode layer, and the second passivation layer is located on the color resist layer, and the second ITO electrode layer is located on the second passivation layer, and the first ITO electrode layer and the second ITO electrode layer are connected to together form the pixel electrode layer.

4. The array substrate according to claim 1 , wherein a material of the source/the drain and the gate is copper or aluminum.

5. The array substrate according to claim 1 , wherein the semiconductor layer is a double layer structure comprising an amorphous silicon layer and a heavy doped N type silicon layer, or a single layer structure comprising an Indium Gallium Zinc Oxide layer.

6. An array substrate, comprising a substrate, a black matrix located on the substrate, a TFT layer located on the black matrix, a color resist layer located on the TFT layer, a second passivation layer and a pixel electrode layer;
wherein the TFT layer comprises a source/a drain located on the black matrix, a semiconductor layer located on the source/the drain, a gate isolation layer located on the semiconductor layer, a gate located on the gate isolation layer and a first passivation layer located on the gate;
wherein the color resist layer is located on the first passivation layer, the second passivation layer is located on the color resist layer, and the pixel electrode layer is located on the second passivation layer, and the array substrate further comprises a via hole penetrating the second passivation layer, the color resist layer, the first passivation layer, the gate isolation layer and the semiconductor layer, and the pixel electrode layer is electrically connected with the source/the drain by the via hole;
wherein a material of the source/the drain and the gate is copper or aluminum; and
wherein the color resist layer is arranged above and separated from the black matrix.

7. The array substrate according to claim 6 , wherein the semiconductor layer is a double layer structure comprising an amorphous silicon layer and a heavy doped N type silicon layer, or a single layer structure comprising an Indium Gallium Zinc Oxide layer.

Assignees

• Shenzhen China Star Optoelect
• Shenzhen China Star Optoelect

Inventors

• Song Liwang

Classifications

• G02F2202/103

  a-Si · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F2001/13685

  Physics · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L29/24

  Electricity · mapped topic