System and method for providing an Ethernet interface

US9800630B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9800630-B2
Application numberUS-201514662860-A
CountryUS
Kind codeB2
Filing dateMar 19, 2015
Priority dateDec 11, 2006
Publication dateOct 24, 2017
Grant dateOct 24, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An apparatus is provided that includes n communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. The blocks are received on the communication channels. Each of the communication channels transmits a different portion of the blocks striped across all of the v virtual lanes. In more particular embodiments, v>=n>=m. The communication media interfaces can be electrical and optical. Each of the communication channels can include a SerDes interface operating at least 5 Gigabits per second. Furthermore, each of the m communication media interfaces is configured to transmit a different stream of information over a single optical fiber.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus, comprising: n electrical communication channels; m optical communication media interfaces, wherein m is less than n; and a plurality of muxes configured to: receive an information stream, the information stream carried over the n electrical communication channels and the m optical communication media interfaces; and transform the information stream from v virtual lanes, each virtual lane comprising a plurality of data blocks from the information stream and an alignment block, wherein at least two virtual lanes are communicated on one electrical communication channel. 2. The apparatus of claim 1 , further comprising a buffer, wherein the v virtual lanes are stored in the buffer. 3. The apparatus of claim 2 , further configured to: identify, in the buffer, the alignment block associated with the virtual lane; and recreate an original data stream using, at least in part, the alignment block. 4. The apparatus of claim 1 , wherein each of the electrical communication channels comprises a SerDes interface operating at at least 5 Gigabits per second. 5. The apparatus of claim 1 , wherein v is a positive integer multiple of the least common multiple of m and n, v being greater than n. 6. The apparatus of claim 1 , wherein n is at least ten and m is less than ten. 7. The apparatus of claim 1 , wherein each of the m optical communication media interfaces is configured to receive a different stream of information over a single optical fiber. 8. The apparatus of claim 1 , further comprising one or more decoding modules for decoding the information stream into the plurality of data blocks using 64B/66B encoding. 9. A method, comprising: receiving an information stream, the information stream carried over n electrical communication channels and m optical communication media interfaces, wherein m is less than n; and transforming the information stream from v virtual lanes, each virtual lane comprising a plurality of data blocks from the information stream and an alignment block, wherein at least two virtual lanes are communicated on one electrical communication channel. 10. The method of claim 9 , wherein the v virtual lanes are stored in a buffer. 11. The method of claim 10 , further comprising: identifying, in the buffer, the alignment block associated with the virtual lane; and recreating an original data stream using, at least in part, the alignment block. 12. The method of claim 9 , wherein each of the electrical communication channels comprises a SerDes interface operating at at least 5 Gigabits per second. 13. The method of claim 9 , wherein v is a positive integer multiple of the least common multiple of m and n, v being greater than n. 14. The method of claim 9 , wherein n is at least ten and m is less than ten. 15. The method of claim 9 , wherein each of the m optical communication media interfaces is configured to receive a different stream of information over a single optical fiber. 16. The method of claim 9 , further comprising decoding the information stream into the plurality of data blocks using 64B/66B encoding. 17. A system, comprising: means for receiving an information stream, the information stream carried over n electrical communication channels and m optical communication media interfaces, wherein m is less than n; and means for transforming the information stream from v virtual lanes, each virtual lane comprising a plurality of data blocks from the information stream and an alignment block, wherein at least two virtual lanes are communicated on one electrical communication channel. 18. The system of claim 17 , wherein the v virtual lanes are stored in a buffer. 19. The system of claim 18 , further comprising: means for identifying, in the buffer, the alignment block associated with the virtual lane; and means for recreating an original data stream using, at least in part, the alignment block. 20. The system of claim 17 , wherein v is a positive integer multiple of the least common multiple of m and n, v being greater than n.

Assignees

Inventors

Classifications

  • Flow control; Congestion control · CPC title

  • H04L47/13Primary

    in a LAN segment, e.g. ring or bus · CPC title

  • Credit based · CPC title

  • Details of coding or modulation · CPC title

  • Gigabit ethernet switching [GBPS] · CPC title

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Frequently asked questions

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What does patent US9800630B2 cover?
An apparatus is provided that includes n communication channels, and m communication media interfaces, and v virtual lanes. V is a positive integer multiple of the least common multiple of m and n. An information stream is transferred into data and alignment blocks striped across all of the v virtual lanes, the blocks being communicated from the virtual lanes onto the communication channels. Th…
Who is the assignee on this patent?
Cisco Tech Inc
What technology area does this patent fall under?
Primary CPC classification H04L47/13. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 24 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).