Circuit for stabilizing a digital-to-analog converter reference voltage

Patent metadata

Field	Value
Publication number	US-9800258-B2
Application number	US-201615373578-A
Country	US
Kind code	B2
Filing date	Dec 9, 2016
Priority date	Dec 17, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

First claim

What is claimed is:

1. A circuit for stabilizing a voltage on a reference node, comprising:
a digital-to-analog converter comprising an array of capacitors and arranged for:
receiving an input voltage (V in ) via an input node;
receiving a voltage (V ref,DAC ) via a reference node and a digital-to-analog code (code DAC ) via a controller node, wherein the digital-to-analog code indicates which capacitors of the array of capacitors to which the voltage (V ref,DAC ) is to be applied; and
outputting a digital-to-analog output voltage (V out );

a capacitive network on the reference node comprising a fixed capacitor (C ref ) arranged to be pre-charged to an external reference voltage (V ref ) and a variable capacitor (C aux ) arranged to be pre-charged to an external auxiliary voltage (V aux ) and afterwards to be connected to the reference node;
a measurement block arranged for measuring the voltage on the reference node; and
a calibration block arranged for receiving the digital-to-analog code and the measured voltage on the reference node and for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

2. The circuit according to claim 1 , wherein the measurement block comprises a comparator arranged to compare the voltage (V ref,DAC ) on the reference node with an external target reference voltage (V ref,target ).

3. The circuit according to claim 1 , wherein the measurement block comprises a comparator with a programmable offset.

4. The circuit according to claim 3 , wherein the programmable offset is set equal to a difference between a target reference voltage (V ref,target ) on the reference node and the external reference voltage.

5. The circuit according to claim 3 , arranged for updating the programmable offset when the variable capacitor (C aux ) reaches a threshold value.

6. The circuit according to claim 1 , wherein the capacitive network further comprises a variable reset capacitor (C aux,rst ) on the reference node arranged for being pre-charged to a second external auxiliary voltage (V aux,rst ) and for being connected to the reference node when the digital-to-analog converter resets.

7. The circuit according to claim 1 , further comprising an additional quantizer for determining the digital-to-analog code.

8. The circuit according to claim 1 , wherein the measurement block comprises an analog-to-digital converter.

9. The circuit according to claim 1 , further comprising storage for storing the updated setting.

10. An analog-to-digital converter, comprising a circuit for stabilizing a voltage on a reference node, wherein the circuit comprises:
a digital-to-analog converter comprising an array of capacitors and arranged for:
receiving an input voltage (V in ) via an input node;
receiving a voltage (V ref,DAC ) via a reference node and a digital-to-analog code (code DAC ) via a controller node, wherein the digital-to-analog code indicates which capacitors of the array of capacitors to which the voltage (V ref,DAC ) is to be applied; and
outputting a digital-to-analog output voltage (V out );

a capacitive network on the reference node comprising a fixed capacitor (C ref ) arranged to be pre-charged to an external reference voltage (V ref ) and a variable capacitor (C aux ) arranged to be pre-charged to an external auxiliary voltage (V aux ) and afterwards to be connected to the reference node;
a measurement block arranged for measuring the voltage on the reference node; and
a calibration block arranged for receiving the digital-to-analog code and the measured voltage on the reference node and for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

11. The analog-to-digital converter, according to claim 10 , wherein the measurement block comprises a comparator arranged to compare the voltage (V ref,DAC ) on the reference node with an external target reference voltage (V ref,target ).

12. The analog-to-digital converter, according to claim 10 , wherein the measurement block comprises a comparator with a programmable offset.

13. The analog-to-digital converter, according to claim 12 , wherein the programmable offset is set equal to a difference between a target reference voltage (V ref,target ) on the reference node and the external reference voltage.

14. The analog-to-digital converter, according to claim 12 , wherein the circuit is arranged for updating the programmable offset when the variable capacitor (C aux ) reaches a threshold value.

15. The analog-to-digital converter, according to claim 10 , wherein the capacitive network further comprises a variable reset capacitor (C aux,rst ) on the reference node arranged for being pre-charged to a second external auxiliary voltage (V aux,rst ) and for being connected to the reference node when the digital-to-analog converter resets.

16. The analog-to-digital converter according to claim 10 , implemented as a successive approximation register analog-to-digital converter, a pipelined analog-to-digital converter, or a pipelined successive approximation register analog-to-digital converter.

17. An analog-to-digital converter, comprising:
a multiplexer; and
a plurality of circuits for stabilizing a voltage on a reference node, wherein each circuit comprises:
a digital-to-analog converter comprising an array of capacitors and arranged for:
receiving an input voltage (V in ) via an input node;
receiving a voltage (V ref,DAC ) via a reference node and a digital-to-analog code (code DAC ) via a controller node, wherein the digital-to-analog code indicates which capacitors of the array of capacitors to which the voltage (V ref,DAC ) is to be applied; and
outputting a digital-to-analog output voltage (V out );

a capacitive network on the reference node comprising a fixed capacitor (C ref ) arranged to be pre-charged to an external reference voltage (V ref ) and a variable capacitor (C aux ) arranged to be pre-charged to an external auxiliary voltage (V aux ) and afterwards to be connected to the reference node;
a measurement block arranged for measuring the voltage on the reference node; and
a calibration block arranged for receiving the digital-to-analog code and the measured voltage on the reference node and for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.

18. The analog-to-digital converter according to claim 17 , wherein the variable capacitor (C aux ) is common to the plurality of circuits and connected via the multiplexer.

19. The analog-to-digital converter according to claim 17 ,
wherein the capacitive network further comprises a variable reset capacitor (C aux,rst ) on the reference node arranged for being pre-charged to a second external auxiliary voltage (V aux,rst ) and for being connected to the reference node when the digital-to-analog converter resets, and
wherein the variable reset capacitor (C aux,rst ) is common to the plurality of circuits and connected via the multiplexer.

20. The analog-to-digital converter according to claim 17 , wherein the measurement block is common to the plurality of circuits and connected via the multiplexer.

Assignees

• Imec Vzw

Inventors

• Martens Ewout
• Craninckx Jan

Classifications

• H03M1/1071

  Measuring or testing · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M1/1061

  using digitally programmable trimming circuits · CPC title

• H03M1/66 Primary

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title