Logic circuit based on spin valves of the spin-polarized supercurrent type and circuit integrating such logic gates

Patent metadata

Field	Value
Publication number	US-9800248-B2
Application number	US-201515311417-A
Country	US
Kind code	B2
Filing date	May 15, 2015
Priority date	May 15, 2014
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

This circuit ( 100 ) includes: an intermediate layer ( 103 ), made from a conductive material and configured according to a pattern; a first electrode and a plurality of electrodes, which includes at least second and third electrodes ( 126, 127, 128 ), each electrode including: A polarizer, made from a ferromagnetic material, placed at a particular point of the pattern of the intermediate layer, and having a magnetization; A superconducting layer, made of a superconducting material, arranged on the polarizer; and a control means ( 112 ) able to modify the magnetization of the polarizer of the second electrode; another control means ( 122 ) able to modify the magnetization of the polarizer of the third electrode; bias terminals for applying a bias signal; and, terminals for measuring an output signal, a level of the output signal being correlated with a mutual orientation of the first, second and third magnetizations.

First claim

The invention claimed is:

1. A logic circuit including:
an intermediate layer, made from an electric current conducting material and configured according to a pattern;
a first electrode and a plurality of electrodes, said plurality of electrodes including at least second and third electrodes;

each electrode including:
A polarizer, made from a ferromagnetic material, placed at a particular point of the pattern of the intermediate layer, and having a magnetization,
A superconducting layer, made from a superconducting material, arranged on a surface of the polarizer opposite a surface of the polarizer in contact with the intermediate layer;
at least one control means modifying the magnetization of the polarizer of an electrode among the second and third electrodes;
at least one other control means modifying the magnetization of the polarizer of the other electrode among the second and third electrodes;

the first and second electrodes on the one hand, and the first and third electrodes on the other hand, making up two spin valves of a spin-polarized supercurrent type,
bias terminals applying a bias signal; and
measuring terminals measuring an output signal,

a level of the output signal being correlated with a mutual orientation of the first, second and third magnetizations.

2. The logic circuit of claim 1 , wherein, the pattern being a band, the first, second and third electrodes are successively arranged along a length of said band, keeping a space between them, and the measuring terminals are arranged at the ends of the band, on either side of the electrodes, the level of the output signal corresponding to a logic “OR” between the magnetizations of the second and third electrodes, the first magnetization being fixed, or complementary to a logic “EQV” between the magnetization of the first, second and third electrodes.

3. The logic circuit of claim 2 , wherein the first and third electrodes each bear a bias terminal for applying the bias signal, which is a current, and the output signal is a voltage measured across the measuring terminals.

4. The logic circuit of claim 1 , wherein the pattern includes:
upstream and downstream portions each made up of a straight band, which is in electrical contact with one of the measuring terminals; and
an intermediate portion made up of a loop-shaped band defining an upper branch and a lower branch,

the first electrode being placed on the upstream portion, the second electrode on the lower branch and the third electrode on the upper branch, the level of the output signal taken across the measuring terminals situated at the ends of the pattern corresponds to a logic “AND” between the magnetizations of the second and third electrodes.

5. The logic circuit of claim 4 , wherein the output signal is a voltage measured across the measuring terminals, and a polarization current is applied between the bias terminals, whereof a first bias terminal is part of the upstream portion, upstream from the first electrode, and whereof a second bias terminal is part of the downstream portion of the circuit, downstream from the electrodes.

6. The logic circuit of claim 1 , wherein the pattern includes:
upstream and downstream portions each made up of a band, which is in electrical contact with one of the measuring terminals, a first electrode being placed on the upstream portion downstream from the measuring terminal, a magnetization of the first electrode corresponding to a logic level C; and
an intermediate portion made up by placing, electrically in parallel, several bands, each band defining a branch, each branch being identified by an integer k, being connected on the one hand to the upstream portion and on the other hand to the downstream portion and bearing an electrode, whose magnetization corresponds to a logic level Vk,

an the level of the output signal taken across the measuring terminals situated at the ends of the pattern corresponds to a logic function NOR(V k ==C) between the magnetizations of the electrodes.

7. The logic circuit of claim 5 , wherein the output signal is a voltage measured across the measuring terminals, and a polarization current is applied between the bias terminals, whereof a first bias terminal is part of the upstream portion, upstream from the first electrode, and whereof a second bias terminal is part of the downstream portion of the circuit, downstream from the electrodes.

8. The logic circuit of claim 1 , the intermediate layer being interrupted by a cutout, the output signal is a current through a resistance connecting the intermediate layer on either side of the cutout, and the bias signal being a bias voltage applied across the bias terminals situated at each end of the pattern.

9. The logic circuit of claim 1 , wherein the superconducting material of the superconducting layers of each electrode is a superconducting material with a high critical temperature.

10. The logic circuit of claim 7 , wherein a thickness of the superconducting layers of each electrode is chosen between 20 and 40 nm.

11. The logic circuit of claim 1 , wherein the ferromagnetic material of the polarizers of each electrode is LCMO.

12. The logic circuit of claim 11 , wherein a thickness of the polarizers of each electrode is chosen between 3 and 10 nm.

13. The logic circuit claim 1 , wherein the material of the intermediate layer is a normal metal, chosen among normal metal oxides and elementary normal metals.

14. The logic circuit of claim 13 , wherein a thickness of the intermediate layer is chosen between 15 and 25 nm.

15. The logic circuit of claim 1 , wherein the substrate is made from a material chosen from among sapphire and SrTiO 3 .

16. The logic circuit claim 1 , wherein a distance between the electrodes and a thickness of the polarizers of the electrodes depend on a charge carrier coherence length in the intermediate layer and a charge carrier coherence length in the polarizers.

17. A circuit including a plurality of logic circuits, wherein each logic circuit is compliant with a logic circuit according to claim 1 .

Assignees

• Thales Sa
• Centre Nat Rech Scient
• Centre Nat De La Rech Scient (C N R S)

Inventors

• Villegas Javier
• Crete Denis

Classifications

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title

• G11C11/44

  using super-conductive elements, e.g. cryotron · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• H03K19/1952 Primary

  with electro-magnetic coupling of the control current · CPC title