Level shifter applicable to low voltage domain to high voltage domain conversion

Patent metadata

Field	Value
Publication number	US-9800246-B2
Application number	US-201514859030-A
Country	US
Kind code	B2
Filing date	Sep 18, 2015
Priority date	Sep 18, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A level shifter includes a latch circuit having a first FET and a second FET; an input circuit having a third FET and a fourth FET, the gates of the first and second FETs being coupled to the drains of the fourth and third FETs, respectively; a first resistive device (resistor, diode-connected FET) coupled between and in series with the first and third FETs between a first voltage rail and a second voltage rail; and a second resistive device (resistor, diode-connected FET) coupled between and in series with the second and fourth FETs between the first and second voltage rails. The gates of the third and fourth FETs are configured to receive a first set of complementary voltages, and a second set of complementary voltages are configured to be generated at the gates of the first and second FETs, respectively. The second set of complementary voltages are based on the first set of complementary voltages.

First claim

What is claimed is:

1. An apparatus, comprising:
a first level shifter configured to receive a first set of complementary voltages and generate therefrom a second set of complementary voltages, wherein the first level shifter comprises:
a first latch circuit comprising a first p-channel field effect transistor (FET) and a p-channel second FET;
a first input circuit comprising a first n-channel FET and a second n-channel FET, wherein gates of the first and second p-channel FETs are coupled to drains of the second and first n-channel FETs, respectively;
a first resistive device coupled between the first p-channel and n-channel FETs, wherein the first p-channel FET, the first resistive device, and the first n-channel FET are coupled in series between a first voltage rail and a second voltage rail;
a second resistive device coupled between the second p-channel and n-channel FETs, wherein the second p-channel FET, the second resistive device, and the second n-channel FET are coupled in series between the first and second voltage rails, wherein gates of the first and second n-channel FETs are configured to receive the first set of complementary voltages, and wherein the second set of complementary voltages are to be generated at the drains of the second and first n-channel FETs, respectively, wherein the second set of complementary voltages includes a high logic voltage that is lower than a voltage at the first voltage rail due to a voltage drop across the first or second resistive device because of current leakage through the first or second n-channel FET, respectively; and

a second level shifter configured to generate a third set of complementary voltages based on the second set of complementary voltages, wherein the second level shifter comprises:
a second latch circuit comprising third and fourth p-channel FETs; and
a second input circuit comprising third and fourth n-channel FETs, wherein gates of the third and fourth p-channel FETs are coupled to drains of the fourth and third p-channel FETs and drains of the third and fourth n-channel FETs, respectively, wherein gates of the third and fourth n-channel FETs are configured to receive the second set of complementary voltages, respectively, wherein the third set of complementary voltages are to be generated at the drains of the fourth and third n-channel FETs, respectively, wherein the third set of complementary voltages includes a high logic voltage substantially the same as the voltage at the first voltage rail.

2. The apparatus of claim 1 , wherein the first set of complementary voltages pertain to a first voltage domain, wherein the third set of complementary voltages pertain to a second voltage domain, and wherein the first voltage domain is different than the second voltage domain.

3. The apparatus of claim 1 , wherein the first resistive device and the second resistive device comprise first and second resistors, respectively.

4. The apparatus of claim 1 , wherein the first resistive device and the second resistive device comprise first and second diode-connected transistors, respectively.

5. The apparatus of claim 1 , wherein:
the first resistive device comprises a fifth p-channel FET including a source coupled to a drain of the first p-channel FET, and gate and drain coupled to the drain of the first n-channel FET; and
the second resistive device comprises a sixth p-channel FET including a source coupled to a drain of the second p-channel FET, and gate and drain coupled to the drain of the second n-channel FET.

6. The apparatus of claim 1 , wherein:
the first resistive device comprises a fifth n-channel FET including drain and gate coupled to a drain of the first p-channel FET, and a source coupled to the drain of the first n-channel FET; and
the second resistive device comprises a sixth p-channel FET including drain and gate coupled to a drain of the second p-channel FET, and a source coupled to the drain of the second n-channel FET.

7. The method of claim 1 , wherein the first resistive device comprises a resistor.

8. The method of claim 1 , wherein the first resistive device comprises a diode-connected transistor.

9. A method, comprising:
generating a first set of complementary high and low voltages at a first node and a second node between first and second voltage rails, respectively, wherein the high voltage of the first set is less than the a voltage on the first voltage rail due to a first voltage drop across a first resistive device because of current leakage through a first n-channel FET;
receiving a second set of complementary high and low voltages at a third node and a fourth node, respectively;
changing the first set of complementary high and low voltages at the first and second nodes to a third set of complementary low and high voltages, respectively, in response to receiving the second set of complementary high and low voltages at the third and fourth nodes, respectively, wherein the high voltage of the third set is less than the voltage on the first voltage rail due to a second voltage drop across a second resistive device because of current leakage through a second n-channel FET, and wherein changing the first set of complementary high and low voltages comprises:
reducing the high voltage at the first node by generating a current through the first resistive device situated between the first voltage rail and the first node; and
increasing the low voltage at the second node by coupling the first voltage rail to the second node in response to the reduction of the high voltage at the first node; and

generating a fourth set of complementary low and high voltages at respective drains of series-connected p-channel and n-channel FET pair in response to changing the first set of complementary high and low voltages at the first and second nodes to the third set of complementary low and high voltages, wherein the high voltage of the fourth set is substantially the same as the voltage at the first voltage rail.

10. The method of claim 9 , further comprising:
receiving a fifth set of complementary high and low voltages at the fourth and third nodes, respectively;
changing the third set of complementary high and low voltages at the second and first nodes to a sixth set of complementary low and high voltages, respectively, in response to receiving the fifth set of complementary high and low voltages at the fourth and third nodes, respectively, wherein the high voltage of the sixth set is less than the voltage on the first rail due to a third voltage drop across the first resistive device because of current leakage through the first n-channel FET, and wherein changing the third set of complementary high and low voltages comprises:
reducing the high voltage at the second node by generating another current through the second resistive device situated between the first voltage rail and the second node; and
increasing the low voltage at the first node by coupling the first voltage rail to the first node in response to the reduction of the high voltage at the second node; and

generating a seventh set of complementary high and low voltages at the respective drains of the series-connected p-channel and n-channel FET pair in response to changing the third set of complementary high and low voltages at the second and first nodes to the sixth set of complementary low and high voltages, wherein the high voltage of the seventh set is substantially the same as the voltage at the first voltage rail.

11. The method of claim 9 , wherein the first set of complementary high and low voltages pertain to a first voltage domain, wherein the fourth set of complementary voltages pertain to a second voltage domain, and wherein the first voltage d

Assignees

• Qualcomm Inc

Inventors

• Roham Masoud
• Meng Yanjie

Classifications

• H03K3/356182

  with additional means for controlling the main nodes · CPC title

• H03K3/35613

  the input circuit having a differential configuration · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title