Systems and methods for implementing error-shaping alias-free asynchronous flipping analog to digital conversion
US-2015365098-A1 · Dec 17, 2015 · US
US9800235B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9800235-B2 |
| Application number | US-201514725001-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 29, 2015 |
| Priority date | Jun 4, 2014 |
| Publication date | Oct 24, 2017 |
| Grant date | Oct 24, 2017 |
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A signal conditioner that includes a transition-detection module and a current-injection module. The transition-detection module is configured to receive a pair of differential signals from a data line and generate one or more comparator output signals and a transition-indication signal to indicate whether a transition has been detected on the differential signals. The current-injection module is configured to receive the comparator output signals and transition-indication signal from the transition-detection module, and generate appropriate currents for injection into the data line to boost edge rates of the differential signals when the transition-detection module detects a transition of the differential signals or remain high impedance when no transition occurs on the differential signals.
Opening claim text (preview).
What is claimed is: 1. A signal conditioner, comprising: a transition-detection module configured to receive a pair of differential signals from a data line and generate a transition-indication signal and a comparator output signal to indicate whether a transition has been detected on the differential signals; and a current-injection module configured to receive the transition-indication signal and the comparator output signal from the transition-detection module, generate currents for injection into the data line to boost edge rates of the differential signals when the transition of the differential signals is detected and remain at high impedance when the differential signals have no transition. 2. The signal conditioner of claim 1 , wherein the comparator output signal comprises first and second comparator output signals, and wherein the transition-detection module comprises: first and second differential comparators coupled with opposite input polarities, the differential comparators configured to receive the differential signals and generate the first and second comparator output signals respectively; and an AND gate configured to receive the first and second comparator output signals and generate the transition-indication signal; wherein the first and second comparators and the AND gate cause the comparator output signals and the transition-indication signal, respectively, to change state as a result of transitions of the differential signals to indicate whether the transition has been detected on the differential signals. 3. The signal conditioner of claim 2 , wherein each of the first and the second differential comparators comprises a differential receiver with an adjustable threshold voltage. 4. The signal conditioner of claim 1 , wherein the current-injection module comprises: a first push-pull driver configured to receive a first pair of gating signals; a second push-pull driver configured to receive a second pair of gating signals; a first blocking switch coupled between output of the first push-pull driver and one differential signal, the first blocking switch configured to receive a third gating signal; a second blocking switch coupled between output of the second push-pull driver and the other differential signal, the second blocking switch configured to receive the third gating signal; wherein the first and second pairs of gating signals are generated based on regulation of the comparator output signal of the transition-detection module; wherein the third gating signal is generated based on the transition-indication signal of the transition-detection module; wherein the first and second push-pull drivers are configured to generate currents for injection through the first and second blocking switches into the data line to boost edge rates of the differential signals when the transition of the differential signals is detected; and wherein the first and second blocking switches remain at high impedance when no transition occurs on the differential signals. 5. The signal conditioner of claim 4 , wherein each of the first and second blocking switches comprises an n-channel MOSFET. 6. The signal conditioner of claim 4 , wherein each of the first and second push-pull drivers comprises a p-channel MOSFET in series with an n-channel MOSFET between a supply voltage and ground. 7. The signal conditioner of claim 6 , wherein the gating signal for the p-channel MOSFET of the first push-pull driver is generated based on regulation of the comparator output signal from the transition-detection module by a first AC-coupled pull-up RC network and a first inverting buffer, and the gating signal for the p-channel MOSFET of the second push-pull driver is generated based on regulation of the comparator output signal from the transition-detection module by a second AC-coupled pull-up RC network and a second inverting buffer. 8. The signal conditioner of claim 6 , wherein the gating signal for the n-channel MOSFET of the first push-pull driver is generated based on regulation of the comparator output signal from the transition-detection module by a first AC-coupled pull-down RC network and a first buffer, and the gating signal for the n-channel MOSFET of the second push-pull driver is generated based on regulation of the comparator output signal from the transition-detection module by a second AC-coupled pull-down RC network and a second buffer. 9. The signal conditioner of claim 7 , wherein each of the first and second AC-coupled pull-up RC networks comprises: a capacitor; a plurality of resistors; and a plurality of switches; wherein, for each of the AC-coupled pull-up RC networks, the capacitor is coupled in series with the gate of the p-channel MOSFET of the push-pull driver; and wherein each of the resistors is in series with and selected by a corresponding one of the switches and, wherein the series combinations of resistors and switches are coupled in parallel between a voltage source and the gate of the p-channel MOSFET of the push-pull driver. 10. The signal conditioner of claim 8 , wherein each of the first and second AC-coupled pull-down RC networks comprises: a capacitor; a plurality of resistors; and a plurality of switches; wherein, for each of the AC-coupled pull-down RC networks, the capacitor is coupled in series with the gate of the n-channel MOSFET of the push-pull driver; and wherein each of the resistors is in series with and selected by a corresponding one of the switches, and wherein the series combinations of resistors and switches are coupled in parallel between a voltage source and the gate of the n-channel MOSFET of the push-pull driver. 11. The signal conditioner of claim 9 , wherein time constants of the first and second AC-coupled pull-up RC networks are configurable through selective control of the plurality of switches. 12. The signal conditioner of claim 10 , wherein the time constants of the first and second AC-coupled pull-down RC networks are configurable, respectively, by changing the resistance of the RC network through control of the switches. 13. The signal conditioner of claim 1 , wherein the comparator output signal includes first and second comparator output signals, and wherein the transition-detection module includes: a plurality of differential comparators coupled with opposite input polarities, the differential comparators are configured to receive the pair of differential signals from the data line and generate the first and second comparator output signals; and a logic gate configured to conjoin the first and second comparator output signals and generate the transition-indication signal, wherein the current-injection module includes: a plurality of push-pull drivers configured to receive gating signals; and a plurality of blocking switches coupled between the push-pull drivers and at least one of the differential signals; wherein differential comparators and the logic gate are configured to cause the first and second comparator output signals and the transition-indication signal, respectively, to change states in correspondence to transitions of the differential signals to indicate whether the transition has been detected on the differential signals; wherein the push-pull drivers are configured to inject the currents into the data line, through the blocking switches, to boost the edge rates of the differential signals based on detection of the transition of the differential signals; and wherein the blocking switches are configured to remain at high impedance when no transition occurs on the differential signals. 14. The signal conditioner of claim 13 , w
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