Signal envelope processing

Patent metadata

Field	Value
Publication number	US-9800206-B2
Application number	US-201615165737-A
Country	US
Kind code	B2
Filing date	May 26, 2016
Priority date	Jul 5, 2013
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Methods and apparatus for detection and tracking of a signal envelope. The circuit comprises absolute value circuitry configured to receive data samples and output a first value corresponding to the magnitude of said data samples. An envelope tracker maintains an envelope output value and compares the first value to the current envelope output value and modifies the envelope output value based on said comparison to provide the envelope output value with predetermined attack and decay characteristics. The absolute value circuitry has a first input for receiving a first digital signal at a first sample rate and a second input for receiving an interpolated version of the first digital signal at a second sample rate which is higher than the first sample rate and outputs the first value based on the magnitudes of the samples received at the first input and the samples received at the second input. Using the first digital signal provides an early indication of any increases in signal envelope whereas the second digital signal can allow a more accurate estimation.

First claim

What is claimed is:

1. An envelope detection circuit comprising:
a first input for receiving a first digital signal at a first sample rate;
a second input for receiving a second digital signal at a second sample rate which is higher than the first sample rate;
a maximum value detector configured to receive samples from both said first input and said second input and maintain a frame maximum value corresponding to the maximum value of any sample received within a frame period; and
an envelope tracker configured to receive the frame maximum value and output an envelope output value.

2. An envelope detection circuit as claimed in claim 1 wherein the second digital signal is an interpolated version of the first digital signal.

3. An envelope detection circuitry as claimed in claim 1 wherein the envelope tracker comprises:
attack circuitry for increasing the envelope output value; and
decay circuitry for decreasing the envelope output value.

4. An envelope detection circuit as claimed in claim 3 wherein the attack circuitry is configured to detect if the frame maximum value is greater than the envelope output value and, if so, to increase the envelope output value to correspond to the frame maximum value.

5. An envelope detection circuit as claimed in claim 3 wherein the decay circuitry is configured to detect if the frame maximum value is lower than the envelope output value for a predetermined number of successive frame periods and, if so, to decrease the envelope output value.

6. An envelope detection circuit as claimed in claim 3 wherein the attack circuitry operates in response to a first clock signal and the decay circuitry operates in response to a frame clock signal which has a rate slower than the first clock signal.

7. An envelope detection circuit as claimed in claim 1 wherein the maximum value detector is configured such that the frame maximum value is updated at any time in a frame period if a sample with a value greater than the current first value is received during the frame period.

8. An envelope detection circuit as claimed in claim 3 wherein the attack circuitry is configured such that the envelope output value may be updated at any time if the frame maximum value increases to a value greater than the current envelope output value during the frame period.

9. An envelope detection circuit as claimed in claim 8 wherein the attack circuitry is configured such that the envelope output value is only increased if the frame maximum value is greater than the envelope output value by a predetermined amount.

10. An envelope detection circuit as claimed in claim 3 wherein the decay circuitry is configured to compare the frame maximum value at the end of a frame period to the envelope output value so as to detect if the frame maximum value was lower than the envelope output value for that frame period.

11. An envelope detection circuit as claimed in claim 1 wherein the second sample rate is at least two times higher than the first sample rate.

12. An envelope detection circuit as claimed in claim 1 wherein the maximum value detector comprises a multiplexor having inputs coupled to said first and second inputs and configured to produce a data stream consisting of samples received from the first input interspersed with samples received from said second input.

13. An envelope detection circuit as claimed in claim 1 comprising at least one pre-emphasis filter arranged to filter the data signals received at least one of the first and second inputs to emphasize any increase in signal level.

14. A signal processing circuit comprising:
an envelope detection circuit as claimed in claim 1 :
a first signal path input for receiving the first digital signal;
a first interpolator configured to interpolate the first digital signal to generate a second digital signal at the second sample rate;
wherein the first input of the envelope detection circuit is configured to receive the first digital signal and the second input of the envelope detector is configured to receive the second digital signal.

15. An electronic device comprising an envelope detection circuit as claimed in claim 1 wherein said device is at least one of: an audio device; a portable device; a communications device; a computing device; a battery powered device; an audio player; a video player; a gaming device; a mobile telephone; a laptop, notebook or tablet computer.

16. An envelope detection circuit comprising:
a first input for receiving a first digital signal at a first sample rate;
a second input for receiving an interpolated version of the first digital signal at a second sample rate which is higher than the first sample rate;
attack circuitry configured to increase an envelope output value if any sample has a value greater than the current envelope output value; and
decay circuitry configured to decrease the envelope output value if no sample has a value greater than the current envelope output value for a predetermined period of time;
wherein the attack circuitry is configured to operate at a first clock speed which is greater than the second sample rate and the decay circuitry is configured to operate at a second clock speed which is slower than the first clock speed.

17. An audio amplifier circuit having a signal path comprising:
a first interpolator configured to receive a digital audio signal and produce an interpolated version at a faster sample rate;
a digital-to-analogue converter downstream in the signal path from the first interpolator;
an analogue amplifier downstream in the signal path from the digital-to-analogue converter;
an envelope detector configured to receive a first signal from the signal path before said first interpolator and a second signal from the signal path before said first interpolator and to produce an envelope value based on the greatest magnitude value of both the first signal and the second signal; and
a controller for controlling at least one setting of at least one component of the amplifier circuit based on said envelope value.

18. An audio amplifier circuit as claimed in claim 17 wherein the envelope detector comprises:
a maximum value detector configured to receive both said first signal and said second signal and maintain a frame maximum value corresponding to the maximum value of any sample of said first or second signal received within a frame period; and
an envelope tracker configured to receive the frame maximum value and output the envelope value.

19. An audio amplifier circuit as claimed in claim 17 wherein said at least one setting comprises at least one of: bias, variable gain setting; switching speed; and switch size.

20. An audio amplifier circuit as claimed in claim 17 comprising a power supply for supplying at least one supply voltage to at least the analogue amplifier wherein said at least one setting comprises at least one of: the supply voltage; the switching speed of the power supply; and the switch size used in the power supply.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Blyth Malcolm
• Mackay Graeme Gordon

Classifications

• H03F3/68

  Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title

• H03F2200/102

  A non-specified detector of a signal envelope being used in an amplifying circuit · CPC title

• H03F1/0227 Primary

  using supply converters · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title

• H03F3/183

  with semiconductor devices only · CPC title