Semiconductor heterostructure with stress management

Patent metadata

Field	Value
Publication number	US-9799793-B2
Application number	US-201615391948-A
Country	US
Kind code	B2
Filing date	Dec 28, 2016
Priority date	Apr 15, 2014
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

First claim

What is claimed is:

1. A heterostructure comprising:
a n-type layer including:
a plurality of intervening sub-layers of a first group III nitride material; and
a plurality of thin sub-layers of a second group III nitride material, wherein the plurality of intervening sub-layers alternate with the plurality of thin sub-layers, wherein the first group III nitride material includes a molar fraction of gallium of at least 0.05, wherein a molar fraction of gallium in the first group III nitride material exceeds the molar fraction of gallium in the second group III nitride material by at least 0.05, and wherein a thickness of each thin sub-layer of the plurality of thin sub-layers is at most five percent of a thickness of each of the plurality of intervening sub-layers located immediately adjacent to each side of the each thin sub-layer of the plurality of thin sub-layers; and

an active region adjacent to the n-type layer, wherein the active region is configured to emit electromagnetic radiation.

2. The heterostructure of claim 1 , further comprising a substrate and a buffer layer located directly on the substrate, wherein the n-type layer is located on the buffer layer.

3. The heterostructure of claim 1 , wherein the plurality of thin sub-layers have a higher frequency closer to the active region.

4. The heterostructure of claim 1 , wherein at least one of: a composition or a thickness of a thin sub-layer in the plurality of thin sub-layers varies laterally.

5. The heterostructure of claim 1 , wherein the first group III nitride material includes aluminum having an aluminum molar fraction of at least 0.1.

6. The heterostructure of claim 1 , wherein the thickness of each of the plurality of intervening sub-layers is between approximately 20 nanometers and approximately 500 nanometers.

7. The heterostructure of claim 1 , wherein the second group III nitride material is aluminum nitride.

8. The heterostructure of claim 1 , wherein the first group III nitride material is Al x Ga 1-x N with 0.4<x<0.7.

9. The heterostructure of claim 1 , wherein the n-type layer includes at least twenty thin sub-layers.

10. A device comprising:
a n-type layer formed of group III nitride materials, wherein the n-type layer includes:
a plurality of intervening sub-layers of a first group III nitride material; and
a plurality of thin sub-layers of a second group III nitride material, wherein the plurality of intervening sub-layers alternate with the plurality of thin sub-layers, wherein the first group III nitride material includes a molar fraction of gallium of at least 0.05, wherein a molar fraction of gallium in the first group III nitride material differs from the molar fraction of gallium in the second group III nitride material by at least 0.05, and wherein a thickness of each thin sub-layer of the plurality of thin sub-layers is at most five percent of a thickness of each of the plurality of intervening sub-layers located immediately adjacent to each side of the each thin sub-layer of the plurality of thin sub-layers, wherein the n-type layer is one of: an n-type contact layer, an n-type cladding layer, or a carrier electronic layer.

11. The device of claim 10 , wherein the device is configured to operate as a light emitting diode, the device further including an active region adjacent to the n-type layer, wherein the n-type layer is one of: the n-type contact layer or the n-type cladding layer.

12. The device of claim 11 , wherein the plurality of intervening sub-layers have a molar fraction of aluminum within approximately twenty percent of a molar fraction of aluminum of a first barrier in the active region adjacent to the n-type layer.

13. The device of claim 10 , wherein the device is configured to operate as a high electron mobility transistor, wherein the n-type layer is a carrier electronic layer.

14. The device of claim 10 , wherein the thickness of each thin sub-layer of the plurality of thin sub-layers is less than a tunneling length of carriers in the n-type layer.

15. The device of claim 10 , wherein the first group III nitride material is AlGaN with a molar fraction of aluminum between 0.4 and 0.7, wherein the second group III nitride material is AlN.

16. The device of claim 10 , wherein at least one of: a composition or a thickness of a thin sub-layer in the plurality of thin sub-layers varies laterally.

17. A method of fabricating a device, the method comprising:
forming a n-type layer on a substrate, wherein the n-type layer includes:
a plurality of intervening sub-layers of a first group III nitride material; and
a plurality of thin sub-layers of a second group III nitride material, wherein the plurality of intervening sub-layers alternate with the plurality of thin sub-layers, wherein the first group III nitride material includes a molar fraction of gallium of at least 0.05, wherein a molar fraction of gallium in the first group III nitride material exceeds the molar fraction of gallium in the second group III nitride material by at least 0.05, and wherein a thickness of each thin sub-layer of the plurality of thin sub-layers is at most five percent of a thickness of each of the plurality of intervening sub-layers located immediately adjacent to each side of the each thin sub-layer of the plurality of thin sub-layers.

18. The method of claim 17 , wherein the first group III nitride material is AlGaN with a molar fraction of aluminum between 0.4 and 0.7, wherein the second group III nitride material is AlN.

19. The method of claim 17 , further comprising selecting the thickness of each of the plurality of intervening sub-layers to limit a sheet resistivity of the n-type layer to no more than fifty percent more than a sheet resistivity of a comparable n-type layer formed of the first group III nitride material, having a same thickness as a thickness of the n-type layer, and including no thin sub-layers.

20. The method of claim 17 , further comprising configuring the plurality of thin sub-layers to reduce an amount of wafer bowing by at least ten percent over a comparable n-type layer formed of the first group III nitride material, having a same thickness as a thickness of the n-type layer, and including no thin sub-layers.

Assignees

• Sensor Electronic Tech Inc
• Sensor Electronics Tech Inc

Inventors

• Billingsley Daniel
• Kennedy Robert M
• Sun Wenhong
• Jain Rakesh
• Shatalov Maxim S
• Dobrinsky Alexander
• Shur Michael
• Gaska Remigijus

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H01L29/7787

  Electricity · mapped topic