Three-dimensional transistor and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9799728-B2
Application number	US-201615224140-A
Country	US
Kind code	B2
Filing date	Jul 29, 2016
Priority date	Aug 25, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

The disclosed subject matter provides a method for fabricating a three-dimensional transistor. The method includes forming an active region and two isolation structures on a semiconductor substrate. The active region is formed between the two isolation structures. The method further includes forming a photoresist layer on the active region and the isolation structures, forming an opening in the photoresist layer to expose a top surface of the active region and a portion of a top surface of each isolation structure, and then forming a trench on each side of the active region by removing a portion of the corresponding isolation structure exposed in the opening through an etching process using the photoresist layer as an etch mask. After the etching process, the portion of the active region between the two trenches becomes a three-dimensional fin structure. The disclosed method simplifies fabrication process for three-dimensional transistors and reduces product cost.

First claim

What is claimed is:

1. A method for fabricating a three-dimensional (3D) transistor, comprising:
providing a semiconductor substrate;
forming an active region and two isolation structures on the semiconductor substrate, wherein the active region is formed between the two isolation structures;
forming a photoresist layer on the active region and the isolation structures;
forming an opening in the photoresist layer to expose a top surface of the active region and a first portion of a top surface of each isolation structure close to the activation region;
forming a trench on each side of the active region by removing a portion of a corresponding isolation structure exposed in the opening through an etching process performed along the opening using the photoresist layer as an etch mask, wherein a portion of the active region between the two trenches becomes a three-dimensional fin structure after etching; and
removing the photoresist layer.

2. The method for fabricating the 3D transistor according to claim 1 , after removing the photoresist layer, further including:
forming a gate dielectric layer on a surface of the fin structure; and
forming a gate electrode to cover the gate dielectric layer by filling the two trenches with a gate material.

3. The method for fabricating the 3D transistor according to claim 1 , wherein:
a top width of the active region is in a range of 0.187 μm to 1.1 μm;
an angle between each sidewall of the active region and a surface of the semiconductor substrate is in a range of 85° to 90°; and
a top width of the isolation structures is in a range of 0.2 μm to 0.4 μm.

4. The method for fabricating the 3D transistor according to claim 1 , wherein:
a width of the first portion of the top surface of each isolation structure is defined as a first width; and
the first width is in a range of 0.18 μm to 0.36 μm.

5. The method for fabricating the 3D transistor according to claim 1 , wherein:
a depth of the trenches is in a range of 440 Å to 2200 Å.

6. The method for fabricating the 3D transistor according to claim 1 , wherein:
a baking temperature for the photoresist layer is in a range of 100° C. to 120° C.

7. The method for fabricating the 3D transistor according to claim 1 , wherein:
a thickness of the photoresist layer is in a range of 3260 Å to 14000 Å.

8. A method for fabricating a 3D transistor, comprising:
providing a semiconductor substrate;
forming an active region and two isolation structures on the semiconductor substrate, wherein the active region is formed between the two isolation structures;
forming a first photoresist layer on the active region and the isolation structures;
forming a first opening in the first photoresist layer on each isolation structure to expose a first portion of a top surface of the isolation structure, wherein the first photoresist layer covers the active region and a portion of each isolation structure close to the active region;
forming a first trench in each isolation structure by removing a portion of the isolation structure exposed in the corresponding first opening through an etching process performed along the first opening using the first photoresist layer as an etch mask, wherein a remaining portion of each isolation structure between the corresponding first trench and the active region becomes a residual structure;
removing the first photoresist layer;
forming a second photoresist layer on the active region and the isolation structures, wherein the second photoresist layer fills up the first trenches;
forming a second opening in the second photoresist layer to expose a top surface of the active region, a top surface of each residual structure, and a portion of each first trench near the corresponding residual structure;
forming a second trench on each side of the active region by removing a portion of the isolation structure exposed in the corresponding second opening through an etching process performed along the second opening by using the second photoresist layer as an etch mask, wherein a portion of the active region exposed by the two second trenches becomes a three-dimensional fin structure; and
removing the second photoresist layer.

9. The method for fabricating the 3D transistor according to claim 8 , after removing the second photoresist layer, further including:
forming a gate dielectric layer on a surface of the fin structure; and
forming a gate electrode to cover the gate dielectric layer by filling the two second trenches with a gate material.

10. The method for fabricating the 3D transistor according to claim 8 , wherein:
a top width of the active region is in a range of 0.187 μm to 1.1 μm;
an angle between each sidewall of the active region and a surface of the semiconductor substrate is in a range of 85° to 90°; and
a top width of the isolation structures is in a range of 0.2 μm to 0.4 μm.

11. The method for fabricating the 3D transistor according to claim 8 , wherein:
a thickness of the first photoresist layer is in a range of 3620 Å to 6700 Å.

12. The method for fabricating the 3D transistor according to claim 8 , wherein:
a width of the first openings is 0.04 μm to 0.08 μm shorter than a top width of the isolation structures.

13. The method for fabricating the 3D transistor according to claim 8 , wherein:
a top width of the residual structures is greater than 0.02 μm.

14. The method for fabricating the 3D transistor according to claim 8 , wherein:
a depth of the first trenches is larger than 40% of a depth of the second trenches.

15. The method for fabricating the 3D transistor according to claim 8 , wherein:
a thickness of the second photoresist layer is in a range of 3620 Å to 6700 Å.

16. The method for fabricating the 3D transistor according to claim 8 , wherein:
a width of the second opening is in a range of 0.507 μm to 1.828 μm.

17. The method for fabricating the 3D transistor according to claim 8 , wherein:
a depth of the second trenches is in a range of 440 Å to 2000 Å.

Assignees

• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg Int Shanghai Corp

Inventors

• Lin Xinyuan
• Jin Ying

Classifications

• H10W10/0145

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10D30/6212

  having fin-shaped semiconductor bodies having non-rectangular cross-sections · CPC title