Resistive random access memory device embedding tunnel insulating layer and memory array using the same and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9799706-B2
Application number	US-201615182640-A
Country	US
Kind code	B2
Filing date	Jun 15, 2016
Priority date	Jul 20, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A resistive random access memory device is provided with a tunneling insulator layer between a resistance change layer and a bottom electrode. Thus, it is possible: to raise the selection (on/off) ratio by the current of a direct tunneling induced by low voltage in the unselected cell and the current of an F-N tunneling induced by high voltage in the selected cell, to efficiently suppress the leakage current in the read operation, to make a low current operation less μA level by controlling the thickness of the tunneling insulator layer, and to be simultaneously fabricated together with circuit devices by forming the bottom electrodes (word lines) with a semiconductor material.

First claim

What is claimed is:

1. A resistive random access memory device comprising:
a bottom electrode formed of a semiconductor material implanted with impurity ions;
a tunneling insulator layer formed on the bottom electrode;
a resistance change layer formed on the tunneling insulator layer; and
a top electrode formed on the resistance change layer.

2. The resistive random access memory device of claim 1 ,
wherein the resistance change layer is formed of a high dielectric (high-k) material having a higher dielectric constant than silicon oxide (SiO 2 ) film, and

wherein the tunneling insulator layer is formed of a silicon oxide film or a low dielectric (low-k) material having a lower dielectric constant than the silicon oxide film and has a thin thickness less than that of the resistance change layer.

3. The resistive random access memory device of claim 1 ,
wherein the semiconductor material is silicon and the resistance change layer is formed of material having traps.

4. The resistive random access memory device of claim 3 ,
wherein the bottom electrode is implanted with p-type impurity ions,
wherein the tunneling insulator layer is formed of one of SiO 2 , carbon-doped silicon dioxide, porous silicon dioxide and HSQ, and
wherein the resistance change layer is formed of one or more of nitride, Pr 1-x Ca x MnO 3 (0≦x≦1), SrTiO 3 , amorphous silicon and carbon.

5. The resistive random access memory device of claim 4 ,
wherein the nitride is Si 3 N 4 and the tunneling insulator layer has a thickness of 2˜3 nm.

6. The resistive random access memory device of claim 2 ,
wherein the semiconductor material is silicon and the resistance change layer is formed of material having traps.

7. The resistive random access memory device of claim 6 ,
wherein the bottom electrode is implanted with p-type impurity ions,
wherein the tunneling insulator layer is formed of one of SiO 2 , carbon-doped silicon dioxide, porous silicon dioxide and HSQ, and
wherein the resistance change layer is formed of one or more of nitride, Pr 1-x Ca x MnO 3 (0≦x≦1), SrTiO 3 , amorphous silicon and carbon.

8. The resistive random access memory device of claim 7 ,
wherein the nitride is Si 3 N 4 and the tunneling insulator layer has a thickness of 2˜3 nm.

9. A memory array using the resistive random access memory device of claim 1 as a unit cell device, comprising:
a semiconductor substrate;
a plurality of the bottom electrodes forming word lines in the semiconductor substrate in a first direction, a separating insulator film being located between the word lines;
the tunneling insulator layer formed on the plurality of word lines;
the resistance change layer formed on the tunneling insulator layer; and
a plurality of the top electrodes forming bit lines on the resistance change layer in a second direction across the word lines.

10. The memory array of claim 9 ,
wherein metal contact plugs are further formed between the resistance changer layer and the bit lines at places where the word lines are across the bit lines.

11. The memory array of claim 9 ,
wherein the resistance change layer is formed of a high dielectric (high-k) material having a higher dielectric constant than silicon oxide (SiO 2 ) film, and
wherein the tunneling insulator layer is formed of a silicon oxide film or a low dielectric (low-k) material having a lower dielectric constant than the silicon oxide film and has a thin thickness less than that of the resistance change layer.

12. The memory array of claim 11 ,
wherein the word lines are implanted with p-type impurity ions,
wherein the tunneling insulator layer is formed of one of SiO 2 , carbon-doped silicon dioxide, porous silicon dioxide and HSQ, and
wherein the resistance change layer is formed of one or more of nitride, Pr 1-x Ca x MnO 3 (0≦x≦1), SrTiO 3 , amorphous silicon and carbon.

13. The memory array of claim 12 ,
wherein the nitride is Si 3 N 4 and the tunneling insulator layer has a thickness of 2˜3 nm.

14. The memory array of claim 10 ,
wherein the resistance change layer is formed of a high dielectric (high-k) material having a higher dielectric constant than silicon oxide (SiO 2 ) film, and
wherein the tunneling insulator layer is formed of a silicon oxide film or a low dielectric (low-k) material having a lower dielectric constant than the silicon oxide film and has a thin thickness less than that of the resistance change layer.

15. The memory array of claim 14 ,
wherein the word lines are implanted with p-type impurity ions,
wherein the tunneling insulator layer is formed of one of SiO 2 , carbon-doped silicon dioxide, porous silicon dioxide and HSQ, and
wherein the resistance change layer is formed of one or more of nitride, Pr 1-x Ca x MnO 3 (0≦x≦1), SrTiO 3 , amorphous silicon and carbon.

16. The memory array of claim 15 ,
wherein the nitride is Si 3 N 4 and the tunneling insulator layer has a thickness of 2˜3 nm.

17. A method for fabricating the memory array of claim 9 , comprising:
a first step of forming the plurality of word lines in the semiconductor substrate by forming the separating insulator films and having an ion implantation;
a second step of forming the tunneling insulator layer on the plurality of word lines by a deposition or oxidation process;
a third step of forming the resistance change layer by a chemical vapor deposition (CVD) process; and
a fourth step of forming the plurality of bit lines on the resistance change layer in the direction across the word lines.

18. The method of claim 17 ,
wherein the semiconductor substrate is a silicon substrate, and
wherein the first step further includes steps of forming and removing a buffer layer formed of silicon oxide film before and after forming the separating insulator films and having the ion implantation, respectively.

19. The method of claim 18 ,
wherein, after having the ion implantation, the separating insulator film is formed by high temperature oxidation and annealing process after exposing the silicon substrate by partially removing the buffer layer at a region to form the separating insulator film.

20. The method of claim 18 ,
wherein the tunneling insulator layer of the second step is formed of silicon oxide film by a low temperature oxidation process, and
wherein the resistance change layer of the third step is continuously formed of silicon nitride (Si 3 N 4 ) film by low pressure chemical vapor deposition (LPCVD) after forming the tunneling insulator layer.

Assignees

• Univ Seoul Nat R & Db Found
• Gachon Univ Of Industry-Academic Coop Found

Inventors

• Park Byung-Gook
• Cho Seongjae
• Kim Sungjun

Classifications

• G11C2213/33

  Material including silicon · CPC title

• G11C2213/54

  Structure including a tunneling barrier layer, the memory effect implying the modification of tunnel barrier conductivity · CPC title

• G11C2213/15

  Current-voltage curve · CPC title

• G11C2013/005

  Read using potential difference applied between cell electrodes · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title