Method for manufacturing active-matrix display panel, and active-matrix display panel

Patent metadata

Field	Value
Publication number	US-9799687-B2
Application number	US-201515320315-A
Country	US
Kind code	B2
Filing date	Jun 10, 2015
Priority date	Jun 19, 2014
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Manufacturing method including forming, over substrate, TFT layer, planarization layer, and display element in this order. Forming of TFT layer involves forming passivation layer to cover TFT layer electrode, such as upper electrode, and to come in contact with planarizing layer. Forming of display element involves forming bottom electrode to come in contact with planarizing layer. TFT layer electrode and bottom electrode are connected by: first forming, in planarizing layer, first contact hole exposing passivation layer at bottom thereof; then forming second contact hole exposing TFT layer electrode at bottom thereof through dry-etching passivation layer exposed at bottom of first contact hole using fluorine-containing gas; then forming liquid repellent film containing fluorine on passivation layer inner surface facing second contact hole; and forming bottom electrode along planarizing layer inner surface and passivation layer inner surface respectively facing first contact hole and second contact hole.

First claim

The invention claimed is:

1. A method of manufacturing an active-matrix display panel, comprising:
forming a thin film transistor (TFT) layer on a substrate;
forming a planarizing layer on the TFT layer; and
forming a display element unit on the planarizing layer, wherein
the forming of the TFT layer includes forming a passivation layer that covers one electrode and that comes into contact with the planarizing layer after forming of the planarizing layer, the one electrode being one of: (i) a source electrode; (ii) a drain electrode; and (iii) a connection electrode connected to the source electrode or the drain electrode,
the forming of the display element unit includes forming a lower electrode that is in contact with the planarizing layer and connects to the one electrode,
connecting the one electrode and the lower electrode involves:
forming, in the planarizing layer, a contact hole that exposes a surface of the passivation layer at the bottom thereof;
forming, in the passivation layer, a contact hole that connects to the contact hole in the planarizing layer and exposes the one electrode at the bottom thereof, through dry-etching the passivation layer exposed at the bottom of the contact hole in the planarizing layer by using a gas containing fluorine;
after forming the contact hole in the passivation layer, forming a liquid-repellent film containing fluorine on an inner wall surface of the passivation layer facing the contact hole in the passivation layer; and
forming the lower electrode along an inner wall surface of the planarizing layer facing the contact hole in the planarizing layer and the inner wall surface of the passivation layer facing the contact hole in the passivation layer.

2. The method of claim 1 , wherein
the liquid-repellent film is formed by continuing to expose the inner wall surface of the passivation layer to the gas after the contact hole in the passivation layer has been formed.

3. The method of claim 2 , wherein
70%× T 0 ≦T 1 ≦150%× T 0

is satisfied, where T 0 denotes an amount of time from the start of the forming of the contact hole in the passivation layer to the completion of the forming of the contact hole in the passivation layer, and
T 1 denotes an amount of time for which the inner wall surface of the passivation layer facing the contact hole in the passivation layer is exposed to the gas in order to form the liquid-repellent film.

4. The method of claim 2 , wherein
the forming of the liquid-repellent film produces an electrode coating film containing fluorine on the surface of the one electrode exposed at the bottom of the contact hole in the passivation layer, and
an amount of time T 1 for which the inner wall surface of the passivation layer facing the contact hole in the passivation layer is exposed to the gas in order to form the liquid-repellent film is set such that a thickness of the electrode coating film does not exceed 3 nm.

5. The method of claim 1 , wherein
after the forming of the liquid-repellent film and before the forming of the lower electrode,
surfaces of the planarizing layer and the passivation layer including regions thereof inside the contact holes are washed by using a washing liquid containing water,
air or a gas is blown onto the surfaces of the planarizing layer and the passivation layer after the washing to remove any washing liquid remaining on the surfaces of the planarizing layer and the passivation layer.

6. The method of claim 1 , wherein
the one electrode is made of copper or a copper alloy.

7. An active-matrix display panel comprising a TFT layer, a planarizing layer, and a display element unit that are formed on a substrate in this order, wherein
the TFT layer includes:
an electrode that is one of: (i) a source electrode; (ii) a drain electrode; and (iii) a connection electrode connected to the source electrode or the drain electrode; and
a passivation layer that covers the electrode and is in contact with the planarizing layer,

the display element unit includes a lower electrode that is in contact with the planarizing layer,
the lower electrode has a portion along inner wall surfaces of the planarizing layer and the passivation layer that face a contact hole so that the lower electrode electrically connects to the electrode at the bottom of the contact hole, the contact hole continuously penetrating the passivation layer and the planarizing layer,
a film containing fluorine is disposed between the lower electrode and the inner wall surfaces, and
an electrode coating film containing fluorine is disposed between the lower electrode and the electrode at the bottom of the contact hole.

8. The active-matrix display panel of claim 7 , wherein
a thickness of the electrode coating film is 3 nm or less.

Assignees

• Joled Inc

Inventors

• Abe Yuuki

Classifications

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P70/15

  by wet cleaning only (H10P70/52 takes precedence) · CPC title

• H10P50/287

  by chemical means · CPC title

• H10P50/283

  by chemical means · CPC title

• H10W20/01

  Manufacture or treatment · CPC title