Semiconductor device

Patent metadata

Field	Value
Publication number	US-9799666-B2
Application number	US-201615063874-A
Country	US
Kind code	B2
Filing date	Mar 8, 2016
Priority date	Feb 19, 2010
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

At least one of a plurality of transistors which are highly integrated in an element is provided with a back gate without increasing the number of manufacturing steps. In an element including a plurality of transistors which are longitudinally stacked, at least a transistor in an upper portion includes a metal oxide having semiconductor characteristics, a same layer as a gate electrode of a transistor in a lower portion is provided to overlap with a channel formation region of the transistor in an upper portion, and part of the same layer as the gate electrode functions as a back gate of the transistor in an upper portion. The transistor in a lower portion which is covered with an insulating layer is subjected to planarization treatment, whereby the gate electrode is exposed and connected to a layer functioning as source and drain electrodes of the transistor in an upper portion.

First claim

The invention claimed is:

1. A semiconductor device comprising a circuit, the circuit comprising:
a first transistor comprising:
a first semiconductor layer;
a first gate insulating layer over the first semiconductor layer; and
a first gate electrode over the first gate insulating layer;

an insulating layer over the first semiconductor layer; and
a second transistor comprising:
a second gate electrode;
a second gate insulating layer over the second gate electrode, the second gate insulating layer comprising part of the insulating layer; and
a second semiconductor layer over the second gate insulating layer,

wherein the first semiconductor layer includes silicon,
wherein the second semiconductor layer includes an oxide semiconductor,
wherein the second gate electrode is formed from a same layer as the first gate electrode, and
wherein the first gate electrode is electrically connected to one of a source and a drain of the second transistor.

2. The semiconductor device according to claim 1 , wherein the first transistor is supported by an SOI substrate.

3. The semiconductor device according to claim 1 , wherein the first transistor is supported by a silicon substrate.

4. The semiconductor device according to claim 1 , wherein the insulating layer has a leveled upper surface.

5. The semiconductor device according to claim 1 , wherein a top surface of the first gate electrode is not covered by the insulating layer.

6. The semiconductor device according to claim 1 , wherein a distance between the second gate electrode and a channel formation region of the second semiconductor layer is equal to a thickness of the first semiconductor layer.

7. The semiconductor device according to claim 1 , wherein the circuit is a memory element.

8. A semiconductor device comprising a circuit, the circuit comprising:
a first transistor comprising:
a first semiconductor layer;
a first gate insulating layer over the first semiconductor layer; and
a first gate electrode over the first gate insulating layer;

an insulating layer over the first semiconductor layer;
a second transistor comprising:
a second gate electrode;
a second gate insulating layer over the second gate electrode, the second gate insulating layer comprising part of the insulating layer; and
a second semiconductor layer over the second gate insulating layer; and

a capacitor comprising:
a first electrode formed from a same layer as the first semiconductor layer; and
a second electrode over the first electrode,

wherein the insulating layer is between the second semiconductor layer and the second gate electrode,
wherein the first semiconductor layer includes silicon,
wherein the second semiconductor layer includes an oxide semiconductor,
wherein the second gate electrode is formed from a same layer as the first gate electrode,
wherein the second electrode is electrically connected to the first gate electrode, and
wherein the second electrode is electrically connected to one of a source and a drain of the second transistor.

9. The semiconductor device according to claim 8 , wherein the second electrode is formed from a same layer as the first gate electrode.

10. The semiconductor device according to claim 8 , wherein the first transistor is supported by an SOI substrate.

11. The semiconductor device according to claim 8 , wherein the first transistor is supported by a silicon substrate.

12. The semiconductor device according to claim 8 , wherein the insulating layer has a leveled upper surface.

13. The semiconductor device according to claim 8 , wherein a top surface of the first gate electrode is not covered by the insulating layer.

14. The semiconductor device according to claim 8 , wherein a distance between the second gate electrode and a channel formation region of the second semiconductor layer is equal to a thickness of the first semiconductor layer.

15. The semiconductor device according to claim 8 , wherein the circuit is a memory element.

16. A semiconductor device comprising a circuit, the circuit comprising:
a first transistor comprising:
a first semiconductor layer;
a first gate insulating layer over the first semiconductor layer; and
a first gate electrode over the first gate insulating layer;

an insulating layer over the first semiconductor layer; and
a second transistor comprising:
a second gate electrode;
a second gate insulating layer over the second gate electrode, the second gate insulating layer comprising part of the insulating layer; and
a second semiconductor layer over the second gate insulating layer,

wherein the first semiconductor layer includes silicon,
wherein the second semiconductor layer includes an oxide semiconductor,
wherein the second gate electrode is formed from a same layer as the first gate electrode,
wherein the circuit is an inverter element,
wherein the first gate electrode is formed from a same layer as the second gate electrode, and
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor.

17. The semiconductor device according to claim 16 , wherein the first transistor is supported by an SOI substrate.

18. The semiconductor device according to claim 16 , wherein the first transistor is supported by a silicon substrate.

19. The semiconductor device according to claim 16 , wherein the insulating layer has a leveled upper surface.

20. The semiconductor device according to claim 16 , wherein a top surface of the first gate electrode is not covered by the insulating layer.

21. The semiconductor device according to claim 16 , wherein a distance between the second gate electrode and a channel formation region of the second semiconductor layer is equal to a thickness of the first semiconductor layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Saito Toshihiko

Classifications

• H01L29/0649

  Electricity · mapped topic

• H01L27/11524 Primary

  Electricity · mapped topic

• H01L29/42328

  Electricity · mapped topic

• H01L29/788

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic