Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9799606-B2
Application number	US-201514637640-A
Country	US
Kind code	B2
Filing date	Mar 4, 2015
Priority date	Apr 7, 2014
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A semiconductor device includes a first conductive pattern on a substrate, an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulation diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first conductive pattern, and a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first conductive pattern on a substrate, the first conductive pattern including, first region conductive patterns on a first region of the substrate, and second region conductive patterns on a second region of the substrate;
an insulating diffusion barrier layer conformally covering a surface of the first conductive pattern, the insulating diffusion barrier layer exposed by an air gap region adjacent to a sidewall of the first region conductive patterns;
a lower interlayer insulating layer filling a space between the second region conductive patterns;
a capping pattern on the lower interlayer insulating layer and the second region conductive patterns; and
a second conductive pattern on the first conductive pattern, the second conductive pattern penetrating the insulating diffusion barrier layer so as to be in contact with the first conductive pattern,
wherein a portion of a bottom surface of the second conductive pattern is exposed by the air gap region, and
wherein the capping pattern does not cover the first region conductive patterns.

2. The semiconductor device of claim 1 , further comprising:
a permeation layer on the insulating diffusion barrier layer; and
an upper interlayer insulating layer on the permeation layer and in contact with a sidewall of the second conductive pattern,
wherein the upper interlayer insulating layer includes a porous layer.

3. The semiconductor device of claim 2 , wherein the upper interlayer insulating layer includes a porous silicon oxy hydrocarbon (SiOCH) layer.

4. The semiconductor device of claim 1 , wherein
the first region conductive patterns are laterally spaced apart from each other at a first distance,
the second region conductive patterns are laterally spaced apart from each other at a second distance greater than the first distance, and
the air gap region is between the first region conductive patterns.

5. The semiconductor device of claim 1 , wherein a mechanical strength of the capping pattern is stronger than a mechanical strength of the lower interlayer insulating layer.

6. The semiconductor device of claim 1 , wherein at least a portion of the second conductive pattern vertically overlaps the air gap region.

7. The semiconductor device of claim 1 , wherein
the first conductive pattern includes a first interconnection portion and a first metal diffusion barrier layer conformally covering at least a sidewall of the first interconnection portion, and
the second conductive pattern includes a second interconnection portion and a second metal diffusion barrier layer surrounding a sidewall and a bottom surface of the second interconnection portion.

8. A semiconductor device comprising:
a plurality of first conductive patterns on a substrate, the plurality of first conductive patterns including,
a plurality of first region conductive patterns on a first region of the substrate, the plurality of first region conductive patterns including air gap regions between adjacent ones of the first region conductive patterns, and
a plurality of second region conductive patterns on a second region of the substrate, the plurality of second region conductive patterns including a porous layer therebetween;

a plurality of second conductive patterns over at least the plurality of first region conductive patterns, at least one of the plurality of second conductive patterns in contact with at least one of the plurality of first region conductive patterns; and
a capping pattern on the plurality of second region conductive patterns and exposing the plurality of first region conductive patterns.

9. The semiconductor device of claim 8 , further comprising:
an insulating diffusion barrier layer conformally covering at least one surface of the plurality of first region conductive patterns,
wherein the insulating diffusion barrier layer and a portion of a bottom surface of the second conductive pattern in contact with the first region conductive patterns are exposed by the air gap regions between the plurality of first region conductive patterns.

10. The semiconductor device of claim 8 , wherein the porous layer between the plurality of second region conductive patterns is a porous silicon oxy hydrocarbon (SiOCH) layer.

11. The semiconductor device of claim 8 , further comprising:
a permeation layer on the insulating diffusion barrier layer; and
an upper interlayer insulating layer on the permeation layer and in contact with a sidewall of the plurality of second conductive patterns,
wherein the upper interlayer insulating layer includes a porous silicon oxy hydrocarbon (SiOCH) layer.

12. The semiconductor device of claim 8 , wherein
the plurality of first region conductive patterns are laterally spaced apart from each other at a first distance, and
the plurality of second region conductive patterns are laterally spaced apart from each other at a second distance greater than the first distance.

13. The semiconductor device of claim 8 , wherein at least a portion of the second conductive pattern in contact with the first region conductive pattern vertically overlaps the air gap regions.

14. The semiconductor device of claim 8 , wherein
at least one of the first conductive patterns includes a first interconnection portion and a first metal diffusion barrier layer conformally covering at least a sidewall of the first interconnection portion, and
at least one of the plurality of second conductive patterns includes a second interconnection portion and a second metal diffusion barrier layer surrounding a sidewall and a bottom surface of the second interconnection portion.

Assignees

• Ahn Sang Hoon
• Rha Sangho
• Baek Jongmin
• You Wookyung
• Lee Nae-In
• Samsung Electronics Co Ltd

Inventors

• Ahn Sang Hoon
• Rha Sangho
• Baek Jongmin
• You Wookyung
• Lee Nae-In

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/084

  for dual-damascene structures · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title