Microstructure, multilayer wiring board, semiconductor package and microstructure manufacturing method

Patent metadata

Field	Value
Publication number	US-9799594-B2
Application number	US-201615219803-A
Country	US
Kind code	B2
Filing date	Jul 26, 2016
Priority date	Jan 27, 2014
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

The present invention is to provide a microstructure capable of improving the withstand voltage of an insulating substrate while securing fine conductive paths, a multilayer wiring board, a semiconductor package, and a microstructure manufacturing method. The microstructure of the present invention has an insulating substrate having a plurality of through holes, and conductive paths consisting of a conductive material containing metal filling the plurality of through holes, in which an average opening diameter of the plurality of through holes is 5 nm to 500 nm, an average value of the shortest distances connecting the through holes adjacent to each other is 10 nm to 300 nm, and a moisture content is 0.005% or less with respect to the total mass of the microstructure.

First claim

What is claimed is:

1. A microstructure comprising:
an insulating substrate having a plurality of through holes; and
conductive paths consisting of a conductive material containing metal filling the plurality of through holes,
wherein an average opening diameter of the plurality of through holes is 5 nm to 500 nm,
an average value of shortest distances connecting the through holes adjacent to each other is 10 nm to 300 nm, and
a moisture content is 0.005% or less with respect to a total mass of the microstructure.

2. The microstructure according to claim 1 ,
wherein the insulating substrate is an aluminum anodized film.

3. The microstructure according to claim 1 that is used as an anisotropic conductive member.

4. A multilayer wiring board comprising:
the microstructure according to claim 3 ; and
a pair of wiring boards disposed to sandwich the microstructure and electrically connected to each other through conductive paths.

5. A semiconductor package using the multilayer wiring board according to claim 4 .

6. A microstructure manufacturing method comprising:
a precursor forming step of providing a plurality of through holes having an average opening diameter of 5 nm to 500 nm in an insulating substrate such that an average value of shortest distances connecting the through holes adjacent to each other is 10 nm to 300 nm, and then filling the plurality of through holes with a conductive material containing metal and forming conductive paths to obtain a precursor; and
a baking treatment step of carrying out a baking treatment at a temperature of 100° C. or higher for 3 hours or longer after the precursor forming step to obtain a microstructure having a moisture content of 0.005% or less with respect to a total mass.

7. The microstructure manufacturing method according to claim 6 ,
wherein the baking treatment step is carried out in a pressure-reduced atmosphere having an oxygen concentration of 0.1% or less.

Assignees

• Fujifilm Corp

Inventors

• Yamashita Kosuke

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title