Semiconductor package substrate having an interfacial layer

Patent metadata

Field	Value
Publication number	US-9799593-B1
Application number	US-201615089026-A
Country	US
Kind code	B1
Filing date	Apr 1, 2016
Priority date	Apr 1, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Semiconductor package substrates and methods of forming semiconductor package substrates are described. In an example, a semiconductor package substrate includes an interfacial layer between a metal layer and a dielectric layer. For example, the interfacial layer may be attached to the metal layer and the dielectric layer by a chemical bond, e.g., a coordinate bond or a covalent bond. Accordingly, the metal layer may adhere to the dielectric layer.

First claim

What is claimed is:

1. A semiconductor package substrate, comprising:
a metal layer including a patterned conductor having a metallic interface surface, wherein the metallic interface surface includes a metal ion;
a dielectric layer including an epoxy resin having a dielectric interface surface; and
an interfacial layer between the metal layer and the dielectric layer, wherein the interfacial layer includes an interfacial layer compound having an end chemically bound to the metal ion of the patterned conductor of the metal layer.

2. The semiconductor package substrate of claim 1 , wherein the dielectric interface surface includes a surface roughness in a range less than 100 nm.

3. The semiconductor package substrate of claim 2 , wherein the metal layer includes a metal deposition having the metal ion on the metallic interface surface.

4. The semiconductor package substrate of claim 3 , wherein the interfacial layer compound is selected from a group consisting of an amine and a thiol, and wherein the end of the interfacial layer compound is chemically bound to the metal ion by one or more of a coordinate bond or a covalent bond.

5. The semiconductor package substrate of claim 4 , wherein the interfacial layer compound has a second end chemically bound to the dielectric layer by a second covalent bond.

6. The semiconductor package substrate of claim 5 , wherein the amine is a triethylenetetramine (TETA) compound, and wherein the second covalent bond is a nitrogen-carbon bond.

7. The semiconductor package substrate of claim 5 , wherein the thiol is a trithiocyanuric acid trisodium salt (TCATS) compound, and wherein the second covalent bond is a sulfur-carbon bond.

8. The semiconductor package substrate of claim 4 , wherein the interfacial layer includes a hydrolyzed chloromethylated aromatic group.

9. A semiconductor package, comprising:
a package substrate including:
a metal layer including a patterned conductor having a metallic interface surface, wherein the metallic interface surface includes a metal ion,
a dielectric layer including an epoxy resin having a dielectric interface surface, and
an interfacial layer between the metal layer and the dielectric layer, wherein the interfacial layer includes an interfacial layer compound having an end chemically bound to the metal ion of the patterned conductor of the metal layer; and

an integrated circuit mounted on the package substrate and electrically connected to the patterned conductor of the metal layer.

10. The semiconductor package of claim 9 , wherein the dielectric interface surface includes a surface roughness in a range less than 100 nm.

11. The semiconductor package of claim 10 , wherein the metal layer includes a metal deposition having the metal ion on the metallic interface surface.

12. The semiconductor package of claim 11 , wherein the interfacial layer compound is selected from a group consisting of an amine and a thiol, and wherein the end of the interfacial layer compound is chemically bound to the metal ion by one or more of a coordinate bond or a covalent bond.

13. The semiconductor package of claim 12 , wherein the interfacial layer includes a hydrolyzed chloromethylated aromatic group.

14. A method, comprising:
applying an interfacial layer to a dielectric interface surface of an epoxy resin of a dielectric film to functionalize the dielectric interface surface, wherein the interfacial layer includes an interfacial layer compound having an end; and
depositing a metal layer including a patterned conductor having a metallic interface surface on the interfacial layer to chemically bond a metal ion of the metallic interface surface to the end of the interfacial layer compound of the interfacial layer such that the metal layer adheres to the functionalized dielectric interface surface of the dielectric film.

15. The method of claim 14 , wherein the dielectric film is partly uncured when the interfacial layer is applied to the dielectric interface surface.

16. The method of claim 15 , wherein functionalizing the dielectric interface surface includes forming covalent bonds between the interfacial layer and the dielectric interface surface.

17. The method of claim 16 , wherein applying the interfacial layer includes dipping the dielectric film in a solution containing an amine to aminate the dielectric interface surface.

18. The method of claim 16 , wherein applying the interfacial layer includes dipping the dielectric film in a solution containing a thiol to thiolate the dielectric interface surface.

19. The method of claim 14 further comprising hydrolyzing an aromatic group on the dielectric interface surface to aminate the dielectric interface surface.

20. The method of claim 19 , wherein applying the interfacial layer includes dipping the dielectric film in a solution containing n-methylol-2-chloroacetamide to chloroamidomethylate the aromatic group, and wherein hydrolyzing the aromatic group includes acid hydrolyzing the chloroamidomethylated aromatic group.

Assignees

• Intel Corp

Inventors

• Bryks Whitney Michael
• Angoua Bainye Francoise
• Seneviratne Dilan Anuradha

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/6525

  for securing the interconnections to the substrate, e.g. to prevent peeling · CPC title

• H10W70/05 Primary

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title