Semiconductor device

Patent metadata

Field	Value
Publication number	US-9799587-B2
Application number	US-201214116432-A
Country	US
Kind code	B2
Filing date	May 16, 2012
Priority date	May 24, 2011
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located closer to the first interlayer insulating film of the second interlayer insulating film, being disposed around the second electrode pad, and being bonded to the first dummy electrode. A second semiconductor device includes: a first semiconductor section including a first electrode, the first electrode being formed on a surface located closer to a bonding interface and extending in a first direction; and a second semiconductor section including a second electrode and disposed to be bonded to the first semiconductor section at the bonding interface, the second electrode being bonded to the first electrode and extending in a second direction that intersects with the first direction.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a first unit;
a second unit, wherein the first and second units are bonded together, and wherein:
the first unit comprises:
a first wiring layer including:
a first interlayer insulating film;
at least one first electrode pad; and
a plurality of first dummy electrodes,
wherein the at least one first electrode pad is embedded in the first interlayer insulating film and has one planar surface located on a same plane as a planar first bonding surface of the first interlayer insulating film,
wherein each of the first dummy electrodes is embedded in the first interlayer insulating film,
wherein each of the first dummy electrodes has one planar surface located on the same plane as the planar first bonding surface of the first interlayer insulating film,
wherein the planar surfaces of the first dummy electrodes are distributed over the first bonding surface,
wherein at least some of the first dummy electrodes are disposed adjacent the at least one first electrode pad, and
wherein a first one of the first dummy electrodes and a second one of the first dummy electrodes are a first distance from an edge of the at least one first electrode pad; and

the second unit comprises:
a photoelectric conversion element; and
a second wiring layer including:
a second interlayer insulating film,
at least one second electrode pad, and
a plurality of second dummy electrodes,
wherein the at least one second electrode pad is embedded in the second interlayer insulating film and has one planar surface located on a same plane as a planar second bonding surface of the second interlayer insulating film that faces the first bonding surface of the first interlayer insulating film,
wherein at least a portion of the one planar surface of the at least one second electrode pad is bonded to at least a portion of the one planar surface of the at least one first electrode pad, at least a portion of the planar surface of one of the first dummy electrodes, or both,
wherein each of the second dummy electrodes is embedded in the second interlayer insulating film,
wherein each of the second dummy electrodes has one planar surface located on the same plane as the planar second bonding surface of the second interlayer insulating film,
wherein the planar surfaces of the second dummy electrodes are distributed over the second bonding surface,
wherein at least some of the second dummy electrodes are disposed adjacent to the at least one second electrode pad, and are bonded to the first dummy electrodes, to the at least one first electrode pad, or both,
wherein the at least one first electrode pad is disposed plane-symmetrically to the at least one second electrode pad with respect to a plane between the first and second units and parallel to the first and second bonding surfaces,
wherein the first dummy electrodes are disposed plane-symmetrically to the second dummy electrodes with respect to a plane between the first unit and the second unit and parallel to the first and second bonding surfaces,
wherein all surfaces of the first dummy electrodes except for the one planar surface located on the same plane as the first bonding surface of the first interlayer insulating film are entirely in contact with the first interlayer insulating film,
wherein all surfaces of the second dummy electrodes except for the one planar surface located on the same plane as the second bonding surface of the second interlayer insulating film are entirely in contact with the second interlayer insulating film, and
wherein the planar surface of at least one of the second dummy electrodes contacts the planar surfaces of two of the first dummy electrodes and a portion of the planar surface of the first interlayer insulating film between the two of the first dummy electrodes.

2. The semiconductor device according to claim 1 , wherein all of the first and second dummy electrodes are electrically isolated.

3. The semiconductor device according to claim 1 , wherein the at least one first electrode pad and the first dummy electrodes have a same bonding surface shape, and are all disposed at equal intervals.

4. The semiconductor device according to claim 1 , wherein the at least one first electrode pad is a plurality of first electrode pads, and wherein the first dummy electrodes are disposed only around one of the first electrode pads.

5. The semiconductor device according to claim 1 , wherein:
the first unit includes a first bonding section and a first wiring line, the first bonding section including the at least one first electrode pad, and the first wiring line being electrically connected to the first bonding section,
the second unit includes a second bonding section and a second wiring line, the second bonding section including the at least one second electrode pad, and the second wiring line being electrically connected to the second bonding section.

6. The semiconductor device according to claim 5 , wherein the at least one first electrode pad is a plurality of first electrodes that are separately connected to the first wiring line.

7. The semiconductor device according to claim 6 , wherein the at least one second electrode pad is a plurality of second electrodes that are separately connected to the second wiring line.

8. The semiconductor device according to claim 6 , wherein the first bonding section includes a first extraction electrode connected to one end of each of the plurality of first electrodes, and the first extraction electrode is electrically connected to the first wiring line.

9. The semiconductor device according to claim 8 , wherein the second bonding section includes a second extraction electrode connected to one end of each of the plurality of second electrodes, and the second extraction electrode is electrically connected to the second wiring line.

10. The semiconductor device according to claim 6 , wherein the first bonding section includes two first extraction electrodes, one of the two first extraction electrodes being connected to one end of each of the plurality of first electrodes, and the other being connected to the other end of each of the plurality of first electrodes, and at least one of the two first extraction electrodes is electrically connected to the first wiring line.

11. The semiconductor device according to claim 10 , wherein the second bonding section includes two second extraction electrodes, one of the two second extraction electrodes being connected to one end of each of the plurality of second electrodes, and the other being connected to the other end of each of the plurality of second electrodes, and at least one of the two second extraction electrodes is electrically connected to the second wiring line.

12. The semiconductor device according to claim 1 , wherein both the first electrodes and the second electrodes are formed of Cu.

13. The semiconductor device of claim 7 , wherein a first barrier film is disposed around at least one of the first electrodes and a second barrier film is disposed around at least one of the second electrodes, and wherein the first and second barrier films are not formed on either the first bonding surface or the second bonding surface.

14. The semiconductor device of claim 1 , wherein the first and second dummy electrodes are made of a metallic material and they are conductively bonded together.

15. The semiconductor device of claim 14 , wherein the first and second dummy electrodes are made of Cu.

16. The semiconductor device of claim 1 , wherein each of the first and second electrode pads is co

Assignees

• Fujii Nobutoshi
• Kagawa Yoshihisa
• Sony Corp

Inventors

• Fujii Nobutoshi
• Kagawa Yoshihisa

Classifications

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/926 Primary

  Multiple bond pads having different sizes · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title