Charge sharing between memory cell plates using a conductive path

Patent metadata

Field	Value
Publication number	US-9799388-B1
Application number	US-201615141491-A
Country	US
Kind code	B1
Filing date	Apr 28, 2016
Priority date	Apr 28, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell.

First claim

What is claimed is:

1. A method of operating a ferroelectric memory array, comprising:
selecting a first ferroelectric memory cell for a first operation, the first ferroelectric memory cell comprising a first ferroelectric capacitor with a first plate;
selecting a second ferroelectric memory cell for a second operation, the second ferroelectric memory cell comprising a second ferroelectric capacitor with a second plate; and
establishing a conductive path between the first plate of the first ferroelectric capacitor and the second plate of the second ferroelectric capacitor during a portion of the second operation and based at least in part on the selection of the first ferroelectric memory cell and the second ferroelectric memory cell.

2. The method of claim 1 , wherein the first operation and the second operation each comprise a write operation or a read operation.

3. The method of claim 1 , further comprising:
determining a time to initiate the second operation of the second ferroelectric memory cell based at least in part on a timing of the first operation of the first ferroelectric memory cell, wherein establishment of the conductive path is based at least in part on the time to initiate the second operation.

4. The method of claim 1 , further comprising:
isolating the first plate from a voltage supply, wherein establishment of the conductive path is after the isolation.

5. The method of claim 1 , further comprising:
isolating the first plate from the second plate; and
shorting the first plate to a voltage reference based at least in part on the isolation.

6. The method of claim 5 , further comprising:
applying a supply voltage to the second plate after the isolation.

7. The method of claim 1 , further comprising:
applying a supply voltage to the second plate after establishment of the conductive path.

8. The method of claim 7 , further comprising:
isolating the first plate from the second plate while the supply voltage is applied to the second plate.

9. The method of claim 1 , further comprising:
determining that a threshold amount of time has elapsed since the establishment of the conductive path; and
isolating the first plate from the second plate based at least in part on the determination that the threshold amount of time has elapsed.

10. The method of claim 1 , further comprising:
determining that a threshold amount of charge has transferred since the establishment of the conductive path; and
isolating the first plate from the second plate based at least in part on the determination that the threshold amount of charge has transferred.

11. A method of operating a ferroelectric memory array, comprising:
performing a first operation of a first ferroelectric memory cell;
performing a second operation of a second ferroelectric memory cell, wherein a timing for the second operation is based at least in part on a timing for the first operation;
activating a first switching component that is in electronic communication with a first plate of the first ferroelectric memory cell and a second plate of the second ferroelectric memory cell based at least in part on the timing for the second operation; and
transferring charge from the first plate to the second plate based at least in part on the activation of the first switching component.

12. The method of claim 11 , further comprising:
determining that a voltage on the second plate resulting from transferring the charge has reached a threshold value; and
isolating the first plate from the second plate based at least in part on the determination.

13. The method of claim 11 , further comprising:
activating a second switching component that is in electronic communication with the first plate of a first ferroelectric cell and the second plate of a second ferroelectric cell, wherein transferring the charge is based at least in part on the activation of the second switching component.

14. The method of claim 11 , further comprising:
selecting the first ferroelectric memory cell using a first word line; and
selecting the second ferroelectric memory cell using a second word line.

15. The method of claim 11 , further comprising:
isolating the first plate from the second plate; and
establishing a conductive path between the first plate and a voltage reference based at least in part on the isolation.

16. The method of claim 15 , further comprising:
establishing a conductive path between the second plate and a voltage supply based at least in part on the establishment of the conductive path between the first plate and the voltage reference.

17. The method of claim 11 , further comprising:
establishing a conductive path between the second plate and a voltage supply while transferring the charge.

18. An electronic memory apparatus, comprising:
a first plate line of a first set of memory cells;
a first pair of switching components comprising a first switching component and a second switching component, the first pair of switching components coupled with the first plate line via a conductive path and coupled with a first driver;
a second pair of switching components comprising a third switching component and a fourth switching component, the second pair of switching components coupled with a second driver different than the first driver;
a second plate line of a second set of memory cells, the second plate line in electronic communication with the first plate line via an equalization line and the first switching component and the third switching component; and
at least one voltage supply in electronic communication with the first plate line and the second plate line.

19. The electronic memory apparatus of claim 18 , wherein the first set of memory cells is in electronic communication with a first word line and wherein the second set of memory cells is in electronic communication with a second word line that is isolated from the first word line.

20. The electronic memory apparatus of claim 18 , wherein the first plate line and the second plate line are each in electronic communication with a first voltage supply and second voltage supply having a greater voltage rating than the first voltage supply.

Assignees

• Micron Technology Inc

Inventors

• Carman Eric S

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C11/221 Primary

  using ferroelectric capacitors · CPC title

• G11C11/225 Primary

  Auxiliary circuits · CPC title

• G11C11/2253

  Address circuits or decoders · CPC title

• G11C11/2273

  Reading or sensing circuits or methods · CPC title