Multi-bit MRAM cell and method for writing and reading to such MRAM cell

Patent metadata

Field	Value
Publication number	US-9799384-B2
Application number	US-201515309229-A
Country	US
Kind code	B2
Filing date	Apr 23, 2015
Priority date	May 9, 2014
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A multi-bit magnetic random access memory (MRAM) cell including a magnetic tunnel junction including: a first magnetic storage layer, a second magnetic storage layer, a magnetic sense layer, a first spacer layer between the first magnetic storage layer and the magnetic sense layer, and a second spacer layer between the second magnetic storage layer and the sense layer. The first and second storage magnetization are switchable between m directions to store data corresponding to one of m 2 logic states, with m>2. The present disclosure further concerns a method for writing and reading to the MRAM cell and to memory devices including multi-bit MRAM cells.

First claim

What is claimed is:

1. A magnetic random access memory (MRAM) cell comprising a magnetic tunnel junction including:
a first magnetic storage layer having a first storage magnetization direction being pinned when the magnetic tunnel junction is at a low threshold temperature and freely switchable when the magnetic tunnel junction is at a first high threshold temperature;
a second magnetic storage layer having a second storage magnetization direction being pinned when the magnetic tunnel junction is at the low threshold temperature and freely switchable when the magnetic tunnel junction is at a second high threshold temperature lower than the first high threshold temperature and higher than the low threshold temperature;
a magnetic sense layer having a sense magnetization that is freely switchable;
a first spacer layer between the first magnetic storage layer and the magnetic sense layer;
a second spacer layer between the second magnetic storage layer and the sense layer;
the first and second storage magnetization being switchable between m directions to store data corresponding to one of m 2 logic states, with m>2.

2. The MRAM cell according to claim 1 , wherein m=16, such that each MRAM cell can store 8-bits.

3. The MRAM cell according to claim 1 ;
further including a first antiferromagnetic layer pinning the first storage magnetization at the low threshold temperature and freeing the first storage magnetization at the first high threshold temperature.

4. The MRAM cell according to claim 3 ;
further including a second antiferromagnetic layer pinning the second storage magnetization at the low threshold temperature and freeing the second storage magnetization at the second high threshold temperature.

5. The MRAM cell according to claim 4 ;
further comprising a bit line electrically coupled to the magnetic tunnel junction;
wherein, during a write operation, the bit line is configured to apply a first heating current to heat the magnetic tunnel junction at the first threshold temperature and to apply a second heating current to heat the magnetic tunnel junction at the second threshold temperature.

6. The MRAM cell according to claim 5 ;
wherein, during a read operation, the bit line is further configured to apply a sense current to determine a resistance of the magnetic tunnel junction.

7. The MRAM cell according to claim 1 ;
further comprising a first field line that is magnetically coupled to the magnetic tunnel junction; and
wherein, during a write operation, the first field line is configured to apply a first write current to induce a first write magnetic field, and the bit line is configured to apply a second write current to induce a second write magnetic field.

8. A method for writing to the MRAM cell according to claim 1 ; the method comprising:
heating the magnetic tunnel junction to a first high threshold temperature such as to unpin the first storage magnetization;
simultaneously or after a short time delay, switching the first storage magnetizations from an initial one of m directions to another one of the m directions;
heating the magnetic tunnel junction at a second high threshold temperature being lower than the first high threshold temperature and higher than the low threshold temperature, such as to pin the first storage magnetization and to unpin the second storage magnetization;
simultaneously or after a short time delay, switching the second storage magnetizations from an initial one of m directions to another one of the m directions.

9. The method according to claim 8 ,
wherein the MRAM cell further comprises a bit line electrically coupled to the magnetic tunnel junction; and
wherein said heating the magnetic tunnel junction to a first and second high threshold temperature comprises applying, respectively, a first heating current and a second heating current through the magnetic tunnel junction via the bit line.

10. The method according to claim 8 ,
wherein the MRAM cell further comprises a first field line that is magnetically coupled to the magnetic tunnel junction; and
wherein said switching the first and second storage magnetizations comprises:
passing a first write current in the first field line such as to induce a first write magnetic field;
passing a second write current in the bit line such as to induce a first write magnetic field;
the first and second storage magnetizations direction being switched in accordance with a resultant write magnetic field corresponding to the combination of the first and second write magnetic fields.

11. The method according to claim 8 ,
further comprising the step of cooling the magnetic tunnel junction to the low threshold temperature.

12. The method according to claim 11 ,
wherein either, or both, of the write magnetic fields are maintained during cooling of the magnetic tunnel junction, and are deactivated once the magnetic tunnel junction has cooled at the low threshold temperature.

13. The method according to claim 8 ,
wherein switching the first and second storage magnetizations is performed by passing a spin-polarized write current in the magnetic tunnel junction, via the bit line.

14. A method of reading the MRAM cell according to claim 1 , wherein the MRAM cell further comprises a bit line and a first field line that are each magnetically coupled to the magnetic tunnel junction; the first field line being configured to apply a first read current to induce a first read magnetic field, and the bit line being configured to apply a second read current to induce a second read magnetic field; the method comprising:
performing a plurality of read cycles, wherein each read cycle comprises aligning the sense magnetization direction relative to the switched direction of the first and second storage magnetization, and measuring a resistance of the magnetic tunnel junction; such as to obtain a resistance response of the magnetic tunnel junction as a function of the sense magnetization direction, wherein the sense magnetization direction is varied in accordance with a resultant read magnetic field corresponding to the combination of the first and second read magnetic fields;
extracting a second local derivative of the resistance response;
from the extracted second local derivative, determining a first angle corresponding the first direction of the first storage magnetization, wherein said determining a first angle comprises locating a first global minimum of the extracted second local derivative; and determining a second angle corresponding the second direction of the second storage magnetization, wherein said determining a second angle comprises, locally fitting the extracted second derivative around the located first global minimum to obtain a fitted global minimum peak, subtracting a portion of the fitted global minimum peak around the first global minimum of the extracted second local derivative such as to obtain a modified second local derivative, and determining the second angle by locating a second global minimum of the modified second local derivative.

15. The method according to claim 14 ,
wherein said locally fitting the extracted second derivative is performed using a peak function, such as a Gaussian function.

16. The method according to claim 14 ,
wherein said portion comprises about 90% of the fitted global minimum peak.

17. The method according to claim 14
further comprising the steps of storing the first angle and the second angle.

18. The method according to claim 14 ,
further comprising matching the first angle and the second an

Assignees

• Crocus Technology Sa

Inventors

• Stainer Quentin

Classifications

• G11C11/1693

  Timing circuits or methods · CPC title

• G11C11/5607

  using magnetic storage elements · CPC title

• G11C11/15

  using multiple magnetic layers (G11C11/155 takes precedence) · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title