Hold time aware register file module and method therefor

Patent metadata

Field	Value
Publication number	US-9799379-B2
Application number	US-201214415153-A
Country	US
Kind code	B2
Filing date	Jul 20, 2012
Priority date	Jul 20, 2012
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.

First claim

The invention claimed is:

1. A device comprising:
an array of latch devices arranged as a plurality of rows and a plurality of columns including a first column, a second column, a first row, and a second row of latch devices, the array of latch devices configured to operate in one of a functional mode wherein each latch device of the array of latch devices provides an addressable memory bit cell, and a scan mode wherein each latch device of the array of latch devices is interconnected to provide at least one scan chain;
an additional column of latch devices including a latch device corresponding to each row of the array of latch devices; and
a clock control component to provide a first clock signal and a second clock signal, the second clock signal an inverted form of the first clock signal, the clock control component to:
if the array of latch devices is operating in the functional mode, provide the first clock signal to each latch included in a selected one of the first column and the second column of latch devices, and provide the second clock signal to each latch in the additional column of latch devices; and
if the array of latch devices is operating in the scan mode, provide the first clock signal to the first column of latch devices and provide the second clock signal to the second column of latch devices.

2. The device of claim 1 , wherein the clock control component is further to provide the first clock signal to the selected one of the first and second column of latch device based on a decoded register address if the array of latch devices is operating in the functional mode.

3. The device of claim 1 , wherein latch devices at the first column of latch devices provides a register, the register selected by a decoded register address if the array of latch devices is operating in the functional mode.

4. The device of claim 3 , wherein an output of a first latch at the additional column of latch devices corresponding to the first row of latch devices is coupled to an input of a second latch device at the first column of latch devices if the decoded register address selects the first column of latch devices.

5. The device of claim 3 , further comprising:
a write port to receive data to be stored at the selected register, the write port coupled to an input of the first latch at the additional column of latch devices.

6. The device of claim 3 , wherein an output of a first latch at the additional column of latch devices corresponding to the first row of latch devices is coupled to a second latch device at the second column of latch devices if the decoded register address selects the second column of latch devices.

7. The device of claim 1 , wherein the first column of latch devices is physically adjacent to the second column of latch devices and physically adjacent to the additional column of latch devices.

8. The device of claim 1 , wherein the first row of latch devices includes a first latch device and a second latch device adjacent to the first latch, and wherein the clock control component is further to, if operating in the scan mode, provide the first clock signal to the first latch device and provide the second clock signal to the second latch device.

9. The device of claim 1 , further comprising:
a read decoder to select one column of the plurality of columns if the array of latch devices is operating in the functional mode, the selecting based on a read address, each latch of selected column corresponding to a respective bit of a register identified by the read address.

10. The device of claim 1 , further comprising:
a write decoder to select one column of the plurality of columns if the array of latch devices is operating in the functional mode, the selecting based on a write address, each latch of selected column corresponding to a respective bit of a register identified by the write address.

11. A method comprising:
determining whether an array of latch devices is operating in a functional mode wherein each latch device of the array of latch devices provides an addressable memory bit cell or a scan mode wherein each latch device of the array of latch devices is interconnected to provide at least one scan chain, the array of latch devices arranged as a plurality of rows and a plurality of columns including a first column, a second column, a first row, and a second row of latch devices;
if the array of latch devices is operating in the functional mode, providing a first clock signal to each latch included in a selected one of the columns of latch devices, and providing a second clock signal that is an inverted form of the first clock signal to each latch in an additional column of latch devices, the additional column of latch devices including a latch device corresponding to each row of the array of latch devices; and
if the array of latch devices is operating in the scan mode, providing the first clock signal to the first column of latch devices and providing the second clock signal to the second column of latch devices.

12. The method of claim 11 , wherein:
each column of latch devices of the array of latch devices provides a register; and
if the array of latch devices is operating in the functional mode, determining the selected one of the plurality of columns of latch devices based on a decoded register address.

13. The method of claim 12 , wherein unselected columns of latch devices do not receive the first clock signal or the second clock signal.

14. The method of claim 12 , further comprising:
receiving data to be stored at the selected register at a write port, the write port coupled to an input of the first latch at the additional column of latch devices.

15. The method of claim 12 , wherein an output of a first latch at the additional column of latch devices corresponding to the first row of latch devices is coupled to an input of a second latch device at the first column of latch devices if the decoded register address selects the first column of latch devices.

16. The method of claim 12 , wherein an output of a first latch at the additional column of latch devices corresponding to the first row of latch devices is coupled to an input of a second latch device at the second column of latch devices if the decoded register address selects the second column of latch devices.

17. The method of claim 11 , wherein an output of a first latch at the first row of latch devices is coupled to an input of a second latch device at the first row of latch devices if the array of latch devices is operating in the scan mode.

18. The method of claim 11 , wherein the first row of latch devices includes a first latch device and a second latch device adjacent to the first latch, the method further comprising, if operating in the scan mode, providing the first clock signal to the first latch device and providing the second clock signal to the second latch device.

19. A register file comprising:
a first column of latch devices to provide a first register;
a second column of latch devices to provide a second register;
a third column of latch devices;
a first row of latch devices;
a second row of latch devices; and
a clock control component to provide a first clock signal and a second clock signal, the second clock signal an inverted form of the first clock signal, the clock control component to:
if the register file is operating in a functional mode wherein each latch device of the first and second columns of latch devices provides an addressable memory bit cell, provide the first clock signal to each latch included in

Assignees

• Priel Michael
• Fleshel Leonid
• Kuzmin Dan
• Nxp Usa Inc

Inventors

• Priel Michael
• Fleshel Leonid
• Kuzmin Dan

Classifications

• G11C19/00

  Digital stores in which the information is moved stepwise, e.g. shift registers · CPC title

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C29/32

  Serial access; Scan testing · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title