Pixel circuit and display panel
US-2024428730-A1 · Dec 26, 2024 · US
US9799266B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9799266-B2 |
| Application number | US-201514844290-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 3, 2015 |
| Priority date | Jan 19, 2015 |
| Publication date | Oct 24, 2017 |
| Grant date | Oct 24, 2017 |
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An organic light-emitting diode display is disclosed. In one aspect, the OLED display includes first and second pixels respectively including first and second capacitors, each of the first and second capacitors including top and bottom electrodes. The first and second pixels respectively include first and second pixel electrodes. The display also includes a substrate, a first conductive layer formed over the substrate and including the bottom electrodes of the first and second capacitors, and a second conductive layer formed over the first conductive layer and including the top electrodes of the first and second capacitors. The display further includes a third conductive layer formed over the second conductive layer and including the first and second pixel electrodes, and a connection node electrically connecting the first capacitor to the second capacitor.
Opening claim text (preview).
What is claimed is: 1. An organic light-emitting diode (OLED) display, the OLED display comprising: first and second pixels respectively including first and second capacitors, wherein each of the first and second capacitors includes top and bottom electrodes, and wherein the first and second pixels respectively include first and second pixel electrodes; a substrate; a first conductive layer formed over the substrate and including the bottom electrodes of the first and second capacitors; a second conductive layer formed over the first conductive layer and including the top electrodes of the first and second capacitors; and a third conductive layer formed over the second conductive layer and including the first and second pixel electrodes, and a connection node extending from the first pixel to the second pixel and interconnecting the first capacitor of the first pixel and the second capacitor of the second pixel, wherein the first and third conductive layers are not in direct physical contact with each other. 2. The OLED display of claim 1 , wherein the first conductive layer comprises a scan line electrically connected to the first and second pixels. 3. The OLED display of claim 1 , wherein the second conductive layer comprises i) a first data line electrically connected to the first pixel and ii) a second data line electrically connected to the second pixel. 4. The OLED display of claim 3 , wherein the connection node is formed over the first and second data lines. 5. The OLED display of claim 1 , wherein the second conductive layer comprises a first power line and a second power line configured to supply power voltages, wherein the first power line is integrally formed with the top electrode of the first capacitor, and wherein the second power line is integrally formed with the top electrode of the second capacitor. 6. The OLED display of claim 1 , wherein the first and second capacitors are adjacent to each other. 7. The OLED display of claim 1 , further comprising an organic insulation layer formed between the second and third conductive layers, wherein the connection node comprises a plurality of contact plugs penetrating through the organic insulation layer and electrically connected to the first and second capacitors. 8. The OLED display of claim 1 , wherein the connection node is formed of at least one of ITO, IZO, ZnO, and In 2 O 3 . 9. The OLED display of claim 1 , further comprising: a first thin-film transistor (TFT) including the bottom electrode of the first capacitor configured to function as a gate electrode; a second TFT including the bottom electrode of the second capacitor configured to function as a gate electrode, wherein each of the first and second TFTs includes an active pattern; and an active layer formed below the first conductive layer and including the active patterns of the first and second TFTs. 10. The OLED display of claim 1 , further comprising: third and fourth pixels respectively comprising third and fourth capacitors, wherein each of the third and fourth capacitors includes a top electrode, wherein the second conductive layer further includes the top electrodes of the third and fourth capacitors, wherein the top electrode of the third capacitor is integrally formed with the top electrode of the first capacitor, and wherein the top electrode of the fourth capacitor is integrally formed with the top electrode of the second capacitor. 11. An organic light-emitting diode (OLED) display comprising: a first pixel comprising a first capacitor including a first bottom electrode and a first top electrode; a second pixel comprising a second capacitor including a second bottom electrode and a second top electrode; a first conductive layer including the first and second bottom electrodes and a connection node extending from the first pixel to the second pixel and interconnecting the first top electrode of the first pixel and the second top electrode of the second pixel; a second conductive layer formed over the first conductive layer and including the first and second top electrodes and a power line configured to supply power voltages to the first and second pixels; and a third conductive layer formed over the second conductive layer, wherein the first and second pixels respectively include first and second pixel electrodes, wherein the third conductive layer includes the first and second pixel electrodes, and wherein the first and third conductive layers are not in direct physical contact with each other. 12. The OLED display of claim 11 , wherein the first conductive layer comprises a scan line electrically connected to the first and second pixels. 13. The OLED display of claim 11 , wherein the second conductive layer comprises i) a first data line electrically connected to the first pixel and ii) a second data line electrically connected to the second pixel. 14. The OLED display of claim 13 , wherein the connection node is formed below the first and second data lines. 15. The OLED display of claim 11 , wherein the connection node is formed apart from the first and second bottom electrodes. 16. The OLED display of claim 11 , wherein the first and second capacitors are adjacent to each other, and wherein the power line is integrally formed with the top electrode of the first capacitor or the top electrode of the second capacitor. 17. The OLED display of claim 11 , further comprising an organic insulation layer formed between the second and third conductive layers, wherein the first and second top electrodes comprise a plurality of contact plugs, and wherein the contact plugs penetrate through the organic insulation layer and are electrically connected to the connection node. 18. The OLED display of claim 11 , further comprising: a first thin-film transistor (TFT) include the bottom electrode of the first capacitor configured to function as a gate electrode; a second TFT include the bottom electrode of the second capacitor configured to function as a gate electrode, wherein each of the first and second TFTs includes an active pattern; and an active layer formed below the first conductive layer and including the active patterns of the first and second TFTs. 19. The OLED display of claim 11 , further comprising: third and fourth pixels respectively comprising third and fourth capacitors, wherein each of the third and fourth capacitors includes a top electrode, wherein the second conductive layer further includes the top electrodes of the third and fourth capacitors, wherein the top electrode of the third capacitor is integrally formed with the top electrode of the first capacitor, and wherein the top electrode of the fourth capacitor is integrally formed with the top electrode of the second capacitor. 20. The OLED display of claim 1 , wherein the top electrodes of the first and second capacitors are not directly connected to each other. 21. The OLED display of claim 1 , wherein neither of the top and bottom electrodes of the first capacitor is shared with the second capacitor.
The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title
Layout of electrodes and connections · CPC title
Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title
used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title
with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title
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