Multiplexed tamper detection system

Patent metadata

Field	Value
Publication number	US-9799180-B1
Application number	US-201615011367-A
Country	US
Kind code	B1
Filing date	Jan 29, 2016
Priority date	Jan 29, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A payment reader includes a tamper detection system for monitoring and protecting against attempts to tamper with the payment reader. The tamper detection system includes tamper detection devices such as tamper switches or tamper meshes, and tamper detection circuitry to control and interface with the tamper detection devices. Pulses are selectively provided from each of a plurality of tamper signal pins of the tamper detection circuitry to an associated tamper detection device, the outputs of the tamper detection devices are multiplexed, the multiplexed signal is received at a tamper detection pin, and a tamper attempt is identified if a pulse was not received within the multiplexed signal. While not transmitting, each of the tamper signal pins is switched to an input state, and a tamper attempt is also identified if any aberrant signal is received at the tamper signal pins while in the input state.

First claim

What is claimed is:

1. A tamper detection system of a payment processing system, comprising:
a first tamper detection device having a first electrical connection point and a second electrical connection point, wherein the first tamper detection device is configured to open a circuit between the first electrical connection point and the second electrical connection point in response to a first tamper event;
a second tamper detection device having a third electrical connection point and a fourth electrical connection point, wherein the second tamper detection device is configured to open a circuit between the third electrical connection point and the fourth electrical connection point in response to a second tamper event;
a first diode, wherein an anode of the first diode is coupled to the second electrical connection point of the first tamper detection device;
a second diode, wherein an anode of the second diode is coupled to the fourth electrical connection point of the second tamper detection device; and
tamper detection circuitry, comprising:
tamper detection logic configured to provide a first sequence of pulses during first time periods and a second sequence of pulses during second time periods;
a first tamper signal pin coupled to the first electrical connection point of the first tamper detection device and configured to output the first sequence of pulses;
a second tamper signal pin coupled to the third electrical connection point of the second tamper detection device and configured to output the second sequence of pulses; and
a tamper detection pin coupled to the cathode of the first diode and the cathode of the second diode, wherein the tamper detection logic is configured to receive a combined signal from the tamper detection pin based on a signal at each of the cathode of the first diode and the cathode of the second diode, and wherein the tamper detection logic is configured to identify the tamper attempt based on a comparison of the combined signal to the first sequence of pulses and the second sequence of pulses.

2. The tamper detection system of claim 1 , wherein each of the first sequence of pulses and the second sequence of pulses comprises a random sequence of pulses or a random sequence of pulse amplitudes.

3. The tamper detection system of claim 1 , further comprising a resistor coupled on one end to a ground and coupled on the other end to the cathode of the first diode, the cathode of the second diode, and the tamper detection pin.

4. The tamper detection system of claim 1 , wherein the first tamper signal pin is configured to operate in an output state during the first time periods and an input state during other time periods, wherein the second tamper signal pin is configured to operate in an output state during the first time periods and an input state during other time periods, and wherein the tamper detection logic is configured to identify the tamper attempt if any electrical signal is received at the first tamper signal pin during its input state or if any electrical signal is received at the second tamper signal pin during its input state.

5. A tamper detection system, comprising:
a first tamper detection device having a first electrical connection point and a second electrical connection point, wherein the first tamper detection device is configured to modify its electrical state in response to a first tamper event;
a second tamper detection device having a third electrical connection point and a fourth electrical connection point, wherein the second tamper detection device is configured to modify its electrical state in response to a second tamper event;
a first blocking component configured to block current flow to the second electrical connection point of the first tamper detection device;
a second blocking component configured to block current flow to the fourth electrical connection point of the second tamper detection device; and
tamper detection circuitry, comprising:
tamper detection logic configured to provide a first sequence of pulses during first time periods and a second sequence of pulses during second time periods;
a first tamper signal pin coupled to the first electrical connection point of the first tamper detection device and configured to output the first sequence of pulses;
a second tamper signal pin coupled to the third electrical connection point of the second tamper detection device and configured to output the second sequence of pulses; and
a tamper detection pin coupled to the first blocking component and the second blocking component, wherein the tamper detection logic is configured to receive a combined signal from the tamper detection pin based on a signal at each of the first blocking component and the second blocking component, and wherein the tamper detection logic is configured to identify a tamper attempt based on a comparison of the combined signal to the first sequence of pulses and the second sequence of pulses.

6. The tamper detection system of claim 5 , wherein the first tamper detection device is configured to modify its electrical state by opening a circuit between the first electrical connection point and the second electrical connection point in response to the first tamper event and wherein the second tamper detection device is configured to modify its electrical state by opening a circuit between the third electrical connection point and the fourth electrical connection point in response to the second tamper event.

7. The tamper detection system of claim 5 , wherein each of the first sequence of pulses and the second sequence of pulses comprises a random sequence of pulses or a random sequence of pulse amplitudes.

8. The tamper detection system of claim 5 , wherein the first tamper signal pin is configured to operate in an output state during the first time periods and an input state during other time periods, wherein the second tamper signal pin is configured to operate in an output state during the second time periods and an input state during other time periods, and wherein the tamper detection logic is configured to identify the tamper attempt based on an electrical signal received at the first tamper signal pin during its input state or based on an electrical signal received at the second tamper signal pin during its input state.

9. The tamper detection system of claim 5 , wherein the first tamper detection device and the second tamper detection device each comprise an anti-tamper mesh.

10. The tamper detection system of claim 5 , wherein the first blocking component comprises a first diode and the second blocking component comprises a second diode.

11. The tamper detection system of claim 10 , further comprising a resistor coupled on one end to ground or power and coupled on the other end to the first diode, the second diode, and the tamper detection pin.

12. The tamper detection system of claim 5 , wherein the first time periods and the second time periods are mutually exclusive.

13. A tamper detection circuitry, comprising:
tamper detection logic configured to provide a first sequence of pulses during first time periods and a second sequence of pulses during second time periods;
a first tamper signal pin configured to output the first sequence of pulses;
a second tamper signal pin configured to output the second sequence of pulses; and
a tamper detection pin coupled to a first blocking component and a second blocking component and configured to receive a combined signal via the first blocking component and the second blocking component, wherein the tamper detection logic is configured to receive the combined signal from the tamper detection pin and to identify a

Assignees

• Square Inc

Inventors

• Rezayee Afshin
• Smith Malcolm
• Yang Yue

Classifications

• G07F7/1008

  Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system · CPC title

• G06F21/554

  involving event detection and direct action · CPC title

• G06Q20/4012 Primary

  Verifying personal identification numbers [PIN] · CPC title

• G06K7/10257

  arrangements for protecting the interrogation against piracy attacks (computer security in general G06F21/00; jamming of communication, countermeasures H04K3/00; secret communication H04K1/00) · CPC title

• G06F21/86

  Secure or tamper-resistant housings · CPC title