Memory controller, method of operating, and apparatus including same

Patent metadata

Field	Value
Publication number	US-9798656-B2
Application number	US-201414309952-A
Country	US
Kind code	B2
Filing date	Jun 20, 2014
Priority date	Jun 28, 2013
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A method of operating a memory controller includes; counting a number of read operations directed to a page-group of data stored in a block and generating a first read count number, then comparing the first read count number with a first reference count threshold among a first set of reference count thresholds associated with the page-group, and upon determining that the first read count number exceeds the first reference count threshold, performing a copy-back operation of the page-group data from the block to another block.

First claim

What is claimed is:

1. A method of operating a memory controller that controls a memory device, the method comprising:
counting a first number of read operations directed to a first page-group of data stored in a first block of the memory device to generate a first read count number, and counting a second number of read operations directed to a second page-group of data stored in the first block of the memory device to generate a second read count number;
comparing the first read count number with a first reference count threshold among a first set of reference count thresholds, and comparing the second read count number with a second reference count threshold among a second set of reference count thresholds;
upon determining that the first read count number exceeds the first reference count threshold, performing a copy-back operation of the first page-group data from the first block to a second block of the memory device different from the first block; and
upon determining that the second read count number exceeds the second reference count threshold, performing the copy-back operation of the second page-group data from the first block to a third block of the memory device different from the first block,
wherein each one of the reference count thresholds in the first set of reference count thresholds is respectively associated with the first page-group and a range of executed program and/or erase (P/E) cycles for the memory device,
each one of the reference count thresholds in the second set of reference count thresholds is respectively associated with the second page-group and a range of executed P/E cycles for the memory device, and
the first page-group data has a lower data reliability expectation than the second page-group data due to read disturbance.

2. The method of claim 1 , wherein the second reference count threshold is different from any reference count threshold in the first set of reference count thresholds.

3. The method of claim 1 wherein the memory device comprises two bit, multi-level memory cells (2-bit MLC), and
the first page-group data is Most Significant Bit (MSB) data and the second page-group data is Least Significant Bit (LSB) data respectively stored in the 2-bit MLC.

4. The method of claim 3 , wherein the first page-group data has a lower data reliability expectation than the second page-group data due to read disturbance.

5. The method of claim 3 , wherein each reference count threshold in the first set of reference count thresholds is respectively lower than a corresponding reference count threshold in the second set of reference count thresholds for each range of executed P/E cycles.

6. The method of claim 5 , wherein each range of executed P/E cycles is defined in a set of ranges of executed P/E cycles, and
each reference count threshold in the first set of reference count thresholds sequentially decreases with each sequential increase in the range of executed P/E cycles.

7. The method of claim 6 , wherein each reference count threshold in the second set of reference count thresholds sequentially decreases with each sequential increase in the range of executed P/E cycles.

8. The method of claim 1 , wherein the memory device is a flash memory device.

9. The method of claim 1 , further comprising:
comparing the third read count number with a third reference count threshold among a third set of reference count thresholds associated with the third page-group; and
upon determining that the third read count number exceeds the third reference count threshold, performing the copy-back operation of the third page-group data from the first block to a fourth block of the memory device different from the first block,
wherein each one of the reference count thresholds in the third set of reference count thresholds is respectively associated with a range of executed P/E cycles for the memory device.

10. The method of claim 9 , wherein the third reference count threshold is different from any reference count threshold in the first and second sets of reference count thresholds.

11. The method of claim 9 , wherein the memory device comprises three bit, multi-level memory cells (3-bit MLC), and
the first page-group data is Most Significant Bit (MSB) data, the second page-group data is Least Significant Bit (LSB) data, and the third page-group data is Center Significant Bit (CSB) data respectively stored in the 3-bit MLC.

12. A memory controller for controlling a memory device and comprising:
a counting module that generates a first read count number for a first page-group of data stored in a first block of a flash memory device, and a second count number for a second page-group of data stored in the first block of the memory device to generate a second read count number; and
a copy-back page-group determination module that compares the first read count number with a first reference count threshold among a first set of reference count thresholds, compares the second read count number with a second reference count threshold among a second set of reference count thresholds, upon determining that the first read count number exceeds the first reference count threshold, performs a copy-back operation of the first page-group data from the first block to a second block of the flash memory device different from the first block, and upon determining that the second read count number exceeds the second reference count threshold, performing the copy-back operation of the second page-group data from the first block to a third block of the memory device different from the first block,
wherein each one of the reference count thresholds in the first set of reference count thresholds is respectively associated with the first page-group and a range of executed program and/or erase (P/E) cycles for the memory device,
each one of the reference count thresholds in the second set of reference count thresholds is respectively associated with the second page-group and a range of executed P/E cycles for the memory device, and
the first page-group data has a lower data reliability expectation than the second page-group data due to read disturbance.

13. The memory controller of claim 12 , wherein the second reference count threshold is different from any reference count threshold in the first set of reference count thresholds.

14. The memory controller of claim 12 , wherein the memory device comprises two bit, multi-level memory cells (2-bit MLC),
the first page-group data is Most Significant Bit (MSB) data and the second page-group data is Least Significant Bit (LSB) data respectively stored in the 2-bit MLC.

15. The memory controller of claim 14 , wherein each reference count threshold in the first set of reference count thresholds is respectively lower than a corresponding reference count threshold in the second set of reference count thresholds for each range of executed P/E cycles.

16. The memory controller of claim 15 , wherein each range of executed P/E cycles is defined in a set of ranges of executed P/E cycles,
each reference count threshold in the first set of reference count thresholds sequentially decreases with each sequential increase in the range of executed P/E cycles, and
each reference count threshold in the second set of reference count thresholds sequentially decreases with each sequential increase in the range of executed P/E cycles.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Won Chul
• Kim Moo Sung

Classifications

• G06F2212/7205

  Cleaning, compaction, garbage collection, erase control · CPC title

• G06F2212/7211

  Wear leveling · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title