Memory mirroring

Patent metadata

Field	Value
Publication number	US-9798628-B2
Application number	US-201414568848-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Apr 25, 2014
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Memory system enabling memory mirroring in single write operations. The memory system includes a memory channel which can store duplicate copies of a data element into multiple locations in the memory channel. The multiple locations are disposed in different memory modules and have different propagation times with respect to a data signal transmitted from the memory controller. In a write operation, the relative timings of the chip select, command and address signals among the multiple locations are adjusted according to the data propagation delay. As a result, a data element can be written into the multiple locations responsive to a data signal transmitted from the memory controller in a single transmission event.

First claim

What is claimed is:

1. A system comprising:
a memory controller; and
a memory channel coupled to said memory controller, said memory channel comprising:
a communication channel directly coupled to said memory controller;
a first dual-inline memory module (DIMM) directly coupled to said communication channel and having a first signal latency for signals sent from the memory controller to the first DIMM; and
a second DIMM directly coupled to said communication channel and having a second signal latency for signals sent from the memory controller to the second DIMM,
wherein said memory controller is configured to enable storage of a primary copy of data within said first DIMM and a secondary copy of the data within said second DIMM in a single write operation by transmitting:
a copy of the data over the memory channel to the first DIMM and the second DIMM;
a first clock signal to the first DIMM; and
a second clock signal to the second DIMM, wherein the second clock signal is delayed with respect to the first clock signal based on the first and second signal latencies.

2. The system of claim 1 , wherein, in said single write operation, said memory controller is further configured to: transmit first write command and address signals to said first DIMM at a first time; and transmit second write command and address signals to said second DIMM at a second time, wherein said second time is delayed with respect to said first time based on the first and second signal latencies.

3. The system of claim 1 , wherein, in said single write operation, said memory controller is further configured to transmit same command and address signals concurrently to said first DIMM and said second DIMM.

4. The system of claim 1 , wherein said first DIMM and said second DIMM are coupled to different command and address buses.

5. The system of claim 1 , wherein, in said single write operation, said first DIMM is configured to start storing said data at a first time, and said second DIMM is configured to start storing said data at a second time, wherein said second time is delayed with respect to said first time based on the first and second signal latencies.

6. The system of claim 1 , wherein, in said single write operation, said memory controller is further configured to transmit a strobe signal concurrently to said first DIMM and said second DIMM.

7. The system of claim 3 , wherein, in said single write operation, said memory controller is further configured to activate chip selects of said first DIMM and said second DIMM respectively and sequentially based on a difference between the first and second signal latencies.

8. A system comprising:
a memory controller; and
a memory channel comprising:
a communication channel directly coupled to said memory controller; and
a plurality of memory modules comprising a first module and a second module, wherein said first module and said second module are directly coupled to said communication channel,

wherein said memory controller is configured to:
determine a propagation delay between said first module and said second module with respect to signals transmitted from said memory controller;
send a data signal representing a data element in a single transmission to said first module and said second module via data buses of said communication channel; and
send clock signals and control signals respectively to said first module and said second module, wherein said clock signals and said control signals are respectively timed based on said propagation delay, and
wherein said first module and said second module each are configured to store said data element responsive to said data signal and said control signals.

9. The system of claim 8 , wherein said first module and said second module are coupled to same command and address buses of said communication channel, and wherein further said memory controller is further configured to send a write command signal in a single transmission to said first module and said second module.

10. The system of claim 8 , wherein said control signals comprise chip select signals and on-die termination signals.

11. The system of claim 8 , wherein said first module is configured to start storing said data element at a first time and said second module is configured to start storing said data element at a second time respectively, and wherein said second time differs from said first time by said propagation delay.

12. The system of claim 8 , wherein said memory controller is integrated in a central processing unit (CPU).

13. The system of claim 8 , wherein said data buses have different trace lengths between said memory controller and said first module and between said memory controller and said second module.

14. The system of claim 8 , wherein said first module comprises a dual in-line memory module (DIMM) and is assigned to store a primary copy of said data element, and wherein further said second module comprises a non-volatile memory module and is assigned to store a backup copy of said data element.

15. The system of claim 8 , wherein said first module and said second module are coupled to separate command and address buses of said communication channel, and wherein further said memory controller is further configured to send write command signals in respective transmissions to said first module and said second module, wherein said respective transmissions are timed based on said propagation delay.

16. A method of storing data by memory mirroring, said method comprising:
receiving at a memory controller a write request for storing a data element;
transmitting by said memory controller a data signal representing said data element in a single write operation to store the data element at a primary memory device and a backup memory device; and
transmitting, by said memory controller over a communication channel directly coupled to said primary memory device, a first control signal at a first time, and transmitting, by said memory controller over the communication channel directly coupled to said backup memory device, a second control signal at a second time that differs from said first time by a propagation delay between said primary and said backup memory device, wherein said first and said second control signals are operable to enable said primary memory device and said backup memory device to store said data element respectively,
wherein said data signal and said first and said second control signals enable storage of a copy of said data element to said primary memory device and a copy of said data element to said backup memory device.

17. The method of claim 16 , wherein said first and said second control signals are chip select signals, and further comprising transmitting a write command signal by said memory controller to said primary memory device and said backup memory device in separate transmissions that are timed based on said propagation delay.

18. The method of claim 16 further comprising transmitting by said memory controller a first clock signal to said primary memory device and a second clock signal to said backup memory device, wherein said first clock signal and said second clock signal are timed based on said propagation delay.

19. The method of claim 16 further comprising transmitting by said memory controller an address signal to said primary memory device and said backup memory in a single transmission via an address bus, wherein said address bus is shared by said primary memory device and said backup memory device.

20. The method of c

Assignees

• Rambus Inc

Inventors

• Woo Steven
• Secker David
• Kollipara Ravindranath

Classifications

• G06F11/1666 Primary

  where the redundant component is memory or memory area · CPC title

• G06F11/2058

  using more than 2 mirrored copies · CPC title

• G06F11/20

  using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements · CPC title

• G06F13/4234

  being a memory bus · CPC title

• G06F11/1456 Primary

  Hardware arrangements for backup · CPC title