Systems and methods for non-blocking solid-state memory

US9798620B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9798620-B2
Application numberUS-201414449787-A
CountryUS
Kind codeB2
Filing dateAug 1, 2014
Priority dateFeb 6, 2014
Publication dateOct 24, 2017
Grant dateOct 24, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Techniques are disclosed relating to writing data across multiple storage blocks in a storage device. In one embodiment, physical erase blocks in a bank of a storage device are erasable. Ones of the physical erase blocks may be associated with different respective communication channels. In such an embodiment, a data stripe may be written across a set of physical erase blocks such that the set of physical erase blocks includes physical erase blocks of different banks and includes physical erase blocks associated with different communication channels. In some embodiments, a request to read a portion of the data stripe may be received. In response to the request, a determination may be made that one of the set of physical erase blocks is unavailable to service the request. The request may then be serviced by reassembling data of the unavailable physical erase block.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus, comprising: a controller; and a plurality of physical buses, each physical bus configured to communicatively couple circuitry of the controller to a respective memory die, the physical buses comprising a plurality of communication channels to physical erase blocks of the respective memory die; wherein the controller is configured to perform erase operations on physical erase blocks arranged into respective erase groups, the erase groups comprising respective sets of physical erase blocks communicatively coupled to the circuitry of the controller through different respective physical buses in parallel, wherein the controller is configured to perform write operations to store data stripes on physical erase blocks arranged into respective write groups, the write groups comprising respective sets of physical erase blocks communicatively coupled to the circuitry of the controller through different respective physical buses in parallel, a write group including a physical erase block included in one or more of the erase groups, wherein the erase groups comprise sets of physical erase blocks different from the sets of physical erase blocks comprising the write groups. 2. The apparatus of claim 1 , wherein, in response to a request to read a portion of a data stripe stored in a write group, the controller is configured to determine that one of the physical erase blocks of the write group is unavailable to service the request, and to service the request by reassembling data of the unavailable physical erase block by use of data read from other physical erase blocks of the write group. 3. The apparatus of claim 2 , wherein determining that the physical erase block is unavailable comprises determining that one or more of the physical erase block, a memory die comprising the physical erase block, and a pad comprising the memory die is occupied servicing one of a write operation and an erase operation. 4. The apparatus of claim 1 , wherein the controller is configured to implement a K-of-N writing scheme, wherein N is a number of physical erase blocks in the write groups, wherein K is a number of physical erase blocks that store data of a data stripe, and wherein N minus K is a number of physical erase blocks in the write groups that store reconstruction metadata of the data stripe, and wherein the data stripe is distributed across physical erase blocks such that K or more physical erase blocks of the data stripe remain available when erase operations are performed on least one of the physical erase blocks. 5. The apparatus of claim 4 , further comprising: a scheduler configured to: track a number of write operations and a number of erase operations performed with respect to the physical erase blocks; and schedule read operations, write operations, and erase operations of the controller such that a number of erase operations and a number of write operations on physical erase blocks of particular write groups do not exceed N minus K within an interval. 6. The apparatus of claim 5 , wherein the scheduler is configured to determine a quality of service to be provided, and to schedule read operations, write operations, and erase operations on physical erase blocks of respective erase groups and write groups to achieve the determined quality of service. 7. The apparatus of claim 4 , wherein N minus K is two or more physical erase blocks. 8. A storage device, comprising: a plurality of memory pads, each memory pad being communicatively coupled to a controller of the storage device through a respective physical bus, the memory pads comprising respective columns of a solid-state storage array, each column comprising a plurality of storage blocks, wherein the storage device is configured to reclaim storage blocks within respective banks of the solid-state storage array concurrently, the banks comprising respective bank groups comprising storage blocks accessible through different respective memory pads and within separate respective columns of the solid-state storage array, wherein the storage device is configured to write data stripes on the solid-state storage array, the data stripes mapping to respective stripe groups comprising storage blocks accessible through different respective memory pads and within separate respective columns of the solid-state storage array such that data stripes are written to storage blocks within a plurality of columns concurrently, wherein a storage block of a stripe group is included in one or more of the bank groups, and wherein the bank groups are different from the stripe groups. 9. The storage device of claim 8 , wherein the banks correspond to rows of the solid-state storage array, and wherein the storage device writes data stripes diagonally within the solid-state storage array. 10. The storage device of claim 8 , wherein the storage device is configured to: track storage blocks being accessed for read operations, write operations, and erase operations; determine that a particular storage block of a data stripe spanning a plurality of storage blocks is being accessed for one or more of a write operation and an erase operation; and reassemble data of the particular storage block from data of the data stripe read from storage blocks of the data stripe. 11. The storage device of claim 10 , wherein the storage device is configured to delay one or more of a write operation or an erase operation in order to read data for reassembling the data of the particular storage block. 12. The storage device of claim 10 , wherein the storage device is configured to reassemble the data of the particular storage block by performing an exclusive-OR operation between data of the data stripe and parity data of the data stripe. 13. The storage device of claim 8 , wherein the storage device is configured to schedule write operations and erase operations such that a number of busy channels does not exceed a threshold and a number of busy storage blocks does not exceed a threshold. 14. The storage device of claim 8 , wherein the data stripe is a data stripe in accordance with redundant array of independent disks (RAID) 5. 15. A method, comprising: performing storage operations on storage elements arranged into an array comprising rows and columns, wherein each column of the array comprises a respective plurality of the storage elements and is communicatively coupled to a controller through a respective physical bus of a plurality of physical buses, wherein the rows of the array comprise storage elements of respective columns, and wherein performing the storage operations comprises: erasing storage elements according to a row pattern within the array, wherein erasing a row according to the row pattern comprises erasing a plurality of storage elements in respective columns of the array, each storage element being erased in response to an erase command received through a respective physical bus; and writing data sets according to a diagonal pattern within the array, wherein writing a data set according to the diagonal pattern comprises writing the data set on storage elements across a plurality of the rows and a plurality of the columns of the array, each column communicatively coupled to the controller through a respective physical bus of the plurality of physical buses of the array, the diagonal pattern different from the row pattern. 16. The method of claim 15 , further comprising: receiving a request to read a portion of a data set written according to the diagonal storage pattern, the portion stored on an inaccessible storage element within a particu

Assignees

Inventors

Classifications

  • Logical to physical mapping or translation of blocks or pages · CPC title

  • Reliability improvement, data loss prevention, degraded operation etc · CPC title

  • G06F11/108Primary

    Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

  • Interfaces specially adapted for storage systems · CPC title

  • in block erasable memory, e.g. flash memory · CPC title

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What does patent US9798620B2 cover?
Techniques are disclosed relating to writing data across multiple storage blocks in a storage device. In one embodiment, physical erase blocks in a bank of a storage device are erasable. Ones of the physical erase blocks may be associated with different respective communication channels. In such an embodiment, a data stripe may be written across a set of physical erase blocks such that the set …
Who is the assignee on this patent?
Sandisk Technologies Llc
What technology area does this patent fall under?
Primary CPC classification G06F11/108. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 24 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).