Transparent user mode scheduling on traditional threading systems

Patent metadata

Field	Value
Publication number	US-9798595-B2
Application number	US-201514960049-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Sep 30, 2008
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Embodiments for performing cooperative user mode scheduling between user mode schedulable (UMS) threads and primary threads are disclosed. In accordance with one embodiment, privileged hardware states are transferred from a kernel portion of a UMS thread to a kernel portion of a primary thread.

First claim

We claim:

1. A system, comprising:
a processor; and
memory communicatively coupled to the processor, the memory comprising:
a register configured to store a pointer to enable creation of a user mode schedulable (UMS) thread based on a standard thread by allowing a user portion and a kernel portion of the standard thread to be independently assigned to the processor;
a context holder to store privileged hardware states of the UMS thread; and
a user mode scheduler executed by the processor to replace first context information of a kernel portion of a primary thread with second context information from a kernel portion of the UMS thread,

wherein the primary thread is executed by the processor to enter kernel mode via a system call and to use the pointer to load the stored privileged hardware states into the kernel portion of the primary thread after the replacement of the first context information with the second context information.

2. The system of claim 1 , wherein the privileged hardware states include debug register states.

3. The system of claim 1 , wherein the user mode scheduler is further executed by the processor to replace the first context information with the second context information using the pointer as the UMS thread is engaged in context saving with the primary thread.

4. The system of claim 3 , wherein user mode scheduler is further executed by the processor to replace the first context information with the second context information in response to a disassociate asynchronous procedure call (APC).

5. A method comprising:
using a pointer, stored in a register, to create a user mode schedulable (UMS) thread based on a standard thread by allowing a user portion and a kernel portion of the standard thread to be independently assigned to a processor;
storing privileged hardware states of the UMS thread;
replacing first context information of a kernel portion of a primary thread with second context information from a kernel portion of the UMS thread;
causing the primary thread to enter kernel mode via a system call; and
loading the stored privileged hardware states into the kernel portion of the primary thread using the pointer after replacing the first context information with the second context information.

6. The method as recited in claim 5 , wherein the primary thread enters kernel mode via a system call.

7. The method of claim 5 , wherein the privileged hardware states include debug register states.

8. The method of claim 5 , wherein the replacing occurs as the UMS thread is engaged in context saving using the pointer with the primary thread.

9. The system of claim 8 , wherein the replacing occurs in response to a disassociate asynchronous procedure call (APC).

10. A system comprising:
one or more processors; and
memory communicatively coupled to the one or more processors, the memory configured to store executable instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
creating a user mode schedulable (UMS) thread based on a standard thread using a pointer stored in a register by allowing a user portion and a kernel portion of the standard thread to be independently assigned to the one or more processors,
storing privileged hardware states of the UMS thread,
replacing first context information of a kernel portion of a primary thread with second context information from a kernel portion of the UMS thread,
causing the primary thread to enter kernel mode via a system call, and
loading the stored privileged hardware states into the kernel portion of the primary thread using the pointer after replacing the first context information with the second context information.

11. The system of claim 10 , wherein the operations further comprise:
causing the primary thread to enter kernel mode via a system call.

12. The system of claim 10 , wherein the privileged hardware states include debug register states.

13. The system of claim 10 , wherein the replacing includes replacing the first context information of the kernel portion of the primary thread with the second context information from the kernel portion of the UMS thread as the UMS thread is engaged in context saving using the pointer with the primary thread.

14. The system of claim 13 , wherein the replacing includes replacing in response to a disassociate asynchronous procedure call (APC).

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Jayamohan Ajith
• Kishan Arun U
• Probert David B
• Teixeira Pedro

Classifications

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/545 Primary

  where tasks reside in different layers, e.g. user- and kernel-space · CPC title

• G06F13/1626

  by reordering requests · CPC title

• G06F9/4843

  by program, e.g. task dispatcher, supervisor, operating system · CPC title

• G06F9/54

  Interprogram communication · CPC title