Migrating pages of different sizes between heterogeneous processors

Patent metadata

Field	Value
Publication number	US-9798487-B2
Application number	US-201615243909-A
Country	US
Kind code	B2
Filing date	Aug 22, 2016
Priority date	Mar 14, 2013
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

One embodiment of the present invention sets forth a computer-implemented method for migrating a memory page from a first memory to a second memory. The method includes determining a first page size supported by the first memory. The method also includes determining a second page size supported by the second memory. The method further includes determining a use history of the memory page based on an entry in a page state directory associated with the memory page. The method also includes migrating the memory page between the first memory and the second memory based on the first page size, the second page size, and the use history.

First claim

What is claimed is:

1. A computer-implemented method for migrating a memory page from a first memory to a second memory, the method comprising:
determining a first page size supported by the first memory associated with a first type of processor;
determining a second page size supported by the second memory associated with a second type of processor that is different from the first type of processor;
determining a use history of the memory page based on a record of accesses of the memory page; and
migrating the memory page between the first memory and the second memory based on the second page size, the first page size, and the use history.

2. The method of claim 1 , wherein the first page size is smaller than the second page size, and migrating the memory page comprises transmitting the memory page from a system memory to a memory local to a parallel processing unit (PPU).

3. The method of claim 2 , further comprising transmitting at least one sibling memory page from the system memory to the memory local to the PPU, wherein the at least one sibling memory page is to be combined with the memory page to generate at least a portion of a larger memory page in the memory local to the PPU.

4. The method of claim 3 , further comprising coalescing an entry in a CPU page table corresponding to the memory page and an entry in the CPU page table corresponding to the at least one sibling memory page to generate an entry in a PPU page table corresponding to the larger memory page.

5. The method of claim 3 , further comprising combining the at least one sibling memory page with the memory page to generate the at least a portion of the large memory page based on an access frequency indicated by the use history of the at least one sibling memory page or the memory page.

6. The method of claim 1 , wherein the first page size is larger than the second page size, and migrating the memory page comprises transmitting a first memory page from a memory local to a parallel processing unit (PPU) to a system memory.

7. The method of claim 6 , wherein migrating the memory page further comprises splitting the memory page in the memory local to the PPU into a plurality of smaller memory pages that includes a second memory page, and transmitting the second memory page from the memory local to the PPU to the system memory.

8. The method of claim 7 , further comprising transmitting all of the other pages in the plurality of smaller memory pages from the memory local to the PPU to the system memory.

9. The method of claim 6 , further comprising removing an entry from a PPU page table corresponding to the memory page.

10. The method of claim 6 , wherein:
the use history indicates that both a CPU and a PPU have recently accessed data included in the first memory page, and, further comprising:
splitting the first memory page, and
transmitting a second memory page from the memory local to the PPU to the system memory.

11. The method of claim 1 , further comprising updating an entry in a page state directory corresponding to the memory page to indicate that the memory page is read-only.

12. The method of claim 1 , wherein migrating the memory page between the first memory and the second memory comprises storing contents of the memory page within a second memory page resident in the second memory, and further comprising updating an entry in a page state directory corresponding to the second memory page to indicate that the second memory page is not accessible.

13. The non-transitory computer-readable medium of claim 12 , further comprising, after migrating the memory page from the first memory to the second memory, updating the entry in the page state directory corresponding to the second memory page to indicate that the second memory page is accessible.

14. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause a computer system to migrate a memory page from a first memory to a second memory, by performing the steps of:
determining a first page size supported by the first memory associated with a first type of processor;
determining a second page size supported by the second memory associated with a second type of processor that is different from the first type of processor;
determining a use history of the memory page based on a record of accesses of the memory page; and
migrating the memory page between the first memory and the second memory based on at least one of the first page size and the second page size as well as the use history.

15. The non-transitory computer-readable medium of claim 14 , wherein the first page size is smaller than the second page size, and migrating the memory page comprises transmitting the memory page from a system memory to a memory local to a parallel processing unit (PPU).

16. The non-transitory computer-readable medium of claim 15 , wherein the instructions further cause the computer system to transmit at least one sibling memory page from the system memory to the memory local to the PPU, wherein the at least one sibling memory page is to be combined with the memory page to generate at least a portion of a larger memory page in the memory local to the PPU.

17. The non-transitory computer-readable medium of claim 14 , wherein the first size is larger than the second page size, and migrating the memory page comprises transmitting a first memory page from a memory local to a parallel processing unit (PPU) to a system memory.

18. The non-transitory computer-readable medium of claim 17 , wherein migrating the memory page further comprises splitting the memory page in the PPU memory into a plurality of smaller memory pages that includes a second memory page, and transmitting the second memory page from the memory local to the PPU to the system memory.

19. The non-transitory computer-readable medium of claim 14 , wherein the memory page has the first page size, and migrating comprises migrating the memory page from the first memory to the second memory, wherein at least a portion of the memory page is stored in the second memory either as an individual memory page or as a portion of a memory page having the second page size.

20. The non-transitory computer-readable medium of claim 14 , wherein migrating comprises performing one or more actions to migrate the memory page from the first memory to the second memory, wherein the one or more actions are based on whether the second page size is smaller than, larger than, or the same size as the first page size.

21. The non-transitory computer-readable medium of claim 14 , wherein the first page size is larger than the second page size, and migrating the memory page comprises transmitting the memory page from a system memory to a memory local to a parallel processing unit (PPU).

22. The non-transitory computer-readable medium of claim 21 , wherein migrating comprises dividing the memory page into a plurality of smaller memory pages, and transmitting the plurality of smaller memory pages from the system memory to the memory local to the PPU.

23. A computing device for migrating a memory page, the computing device comprising:
a first memory;
a second memory; and
a processor that, when executing a unified virtual memory (UVM) driver, is configured to:
determine a first page size supported by the first memory associated with a first type of processor;
determine a second page size supported by the second memory associated with a second type of processor that is different

Assignees

• Nvidia Corp

Inventors

• Duluk Jr Jerome F
• Buschardt Cameron
• Deming James Leroy
• Dunning Lucien
• Fahs Brian
• Hairgrove Mark
• Jia Chenghuan
• Mashey John
• Van Dyke James M

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F2212/652

  Page size control · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/08 Primary

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F12/122

  of the least frequently used [LFU] type, e.g. with individual count value · CPC title