Indicating critical battery status in mobile devices

Patent metadata

Field	Value
Publication number	US-9798369-B2
Application number	US-201615079331-A
Country	US
Kind code	B2
Filing date	Mar 24, 2016
Priority date	Mar 8, 2013
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores;
a static memory;
a power controller to generate a status indicator if a charge on a battery decreases to a minimally charged level;
a controller coupled to the power controller to detect occurrence of the status indicator, generate a request to the power controller to power on a first portion of the processor, and cause battery status data stored in a memory to be transferred to the static memory; and
a display controller to retrieve the battery status data from the static memory and render the battery status data in a visual form for display on a display, wherein the first portion includes the static memory and the display controller.

2. The processor of claim 1 , further comprising a display driver to write configuration values into one or more configuration registers in response to receipt of a signal from the controller.

3. The processor of claim 2 , wherein the display controller is to determine that the battery status data is to be retrieved from the static memory based on the configuration values.

4. The processor of claim 1 , wherein the power controller is to generate the status indicator during a boot sequence, and prevent the plurality of cores from being powered on.

5. The processor of claim 1 , wherein the processor comprises a system on chip (SoC).

6. The processor of claim 5 , wherein the SoC further comprises an integrated memory controller, one or more media processors and the memory, the memory comprising a dynamic random access memory.

7. The processor of claim 1 , wherein the static memory further comprises a control unit and one or more memory blocks to store the battery status data.

8. The processor of claim 1 , wherein the first portion of the processor further comprises the controller.

9. The processor of claim 8 , wherein the power controller is to power on the controller, the display controller and the static memory responsive to a receipt of the request from the controller.

10. The processor of claim 2 , wherein the one or more configuration registers include a first register, wherein the first register includes a power indication bit (PIB), a static random access memory identifier (SRAM ID) field, a start address (STRT ADDR) field, and an end address (END ADDR) field, wherein the SRAM ID field is to store an identifier of the static memory, the STRT ADDR field is to store a starting address of memory blocks from which the battery status data is to be retrieved, and the END ADDR field is to store a last address of the memory blocks to store the battery status data.

11. The processor of claim 1 , wherein the display controller is to store the battery status data obtained from the static memory in a frame buffer.

12. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
generating a status indicator in response to detecting a battery charge level below a threshold;
sending identifiers of one or more blocks of a processor to be powered on in response to occurrence of the status indicator;
powering on the one or more blocks based on the identifiers of the one or more blocks, wherein the one or more blocks include a static memory of the processor and a display unit;
storing battery status data in the static memory;
configuring a first register to cause the battery status data to be retrieved from the static memory;
configuring a power indicator of a second register with a second value to indicate that configuration values in other fields of the second register are invalid, wherein the other fields include a field to store an identifier of a dynamic memory of the processor;
retrieving the battery status data from the static memory and storing the battery status data into a frame buffer; and
displaying on a display a battery status in a visual form to indicate that a battery is being charged.

13. The non-transitory machine-readable medium of claim 12 , wherein the method further comprises displaying a battery symbol on the display to indicate to a user that the battery is being charged.

14. The non-transitory machine-readable medium of claim 12 , wherein the method further comprises checking the battery charge level at regular intervals.

15. The non-transitory machine-readable medium of claim 14 , wherein the method further comprises resuming a boot sequence responsive to the battery charge level exceeding the threshold.

16. The non-transitory machine-readable medium of claim 12 , wherein the method further comprises powering on at least a host processor, a dynamic memory, and a system agent of the processor in response to receiving an input from a user.

17. The non-transitory machine-readable medium of claim 12 , wherein configuring the first register includes configuring a power indicator of the first register with a first value to indicate that configuration values in other fields of the first register are valid, configuring a static memory identifier field with an identifier of the static memory, configuring a start address field and an end address field, respectively, with a starting address and a last address of memory blocks in which the battery status data is stored.

18. A mobile device comprising:
a system on chip (SoC) comprising:
a plurality of cores;
a static memory;
a power controller to generate a status indicator if a charge on a battery decreases to a minimally charged level;
a controller coupled to the power controller to detect occurrence of the status indicator, generate a request to the power controller to power on a first portion of the SoC, and cause battery status data stored in a memory to be transferred to the static memory; and
a display controller to retrieve the battery status data from the static memory and render the battery status data in a visual form for display on a display, wherein the first portion includes the static memory and the display controller; and

the display coupled to the SoC.

19. The mobile device of claim 18 , wherein the mobile device comprises a smart phone.

20. The mobile device of claim 18 , wherein the battery status data is to indicate that the battery is in a charge cycle.

Assignees

• Intel Corp

Inventors

• Herrera Mejia Ivan
• Shoemaker Kenneth D
• Wells Ryan D

Classifications

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F1/30 Primary

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

• G06F9/4406

  Loading of operating system · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F11/00

  Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) · CPC title