Circuit layout for improving power supply rejection ratio
US-2024094752-A1 · Mar 21, 2024 · US
US9798339B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9798339-B2 |
| Application number | US-201314438941-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 30, 2013 |
| Priority date | Oct 30, 2012 |
| Publication date | Oct 24, 2017 |
| Grant date | Oct 24, 2017 |
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A technique is provided that reduces dullness of a potential provided to a line such as gate line on an active-matrix substrate to enable driving the line at high speed and, at the same time, reduces the size of the picture frame region. On an active-matrix substrate ( 20 a ) are provided gate lines ( 13 G) and source lines. On the active-matrix substrate ( 20 a ) are further provided: gate drivers ( 11 ) each including a plurality of switching elements, at least one of which is located in a pixel region, for supplying a scan signal to a gate line ( 13 G); and lines ( 15 L 1 ) each for supplying a control signal to the associated gate driver ( 11 ). A control signal is supplied by a display control circuit ( 4 ) located outside the display region to the gate drivers ( 11 ) via the lines ( 15 L 1 ). In response to a control signal supplied, each gate driver ( 11 ) drives the gate line ( 13 G) to which it is connected.
Opening claim text (preview).
The invention claimed is: 1. An active-matrix substrate comprising: a plurality of data lines; a plurality of lines crossing the plurality of data lines and including at least gate lines; a plurality of control signal lines in a display region that includes pixel regions defined by the data lines and the gate lines, the plurality of control signal lines being provided with a control signal from outside the display region; and a driving circuit including a plurality of switching elements connected to the plurality of control signal lines, the driving circuit being connected to at least one of the gate lines through a first connection and applying one of a selection voltage and a non-selection voltage to the at least one of the gate lines by driving the plurality of switching elements in response to the control signal, wherein the driving circuit is connected to the at least one of the gate lines through a second connection and controls a potential of the at least one of the gate lines by applying another one of the selection voltage and the non-selection voltage to the at least one of the gate lines in response to the control signal, a plurality of the driving circuits is provided for each one of the gate lines, one of the pixel regions includes a pixel electrode connected to one of the gate lines and one of the data lines, and an auxiliary capacitance electrode connected to the pixel electrode, the active-matrix substrate further comprises: an auxiliary capacitance line outside the display region and connected to the auxiliary capacitance electrode to supply a predetermined potential to the auxiliary capacitance electrode; and a low-impedance line in the one of the pixel regions and connected to the auxiliary capacitance electrode and the auxiliary capacitance line. 2. The active-matrix substrate according to claim 1 , further comprising: a pixel electrode in one of the pixel regions and connected to one of the gate lines and one of the data lines, wherein a shield layer made of transparent conductive film is between one of the switching elements in the one of the pixel regions, and the pixel electrode. 3. The active-matrix substrate according to claim 1 , further comprising: a pixel electrode in one of the pixel regions and connected to one of the gate lines and one of the data lines, wherein one of the switching elements in the one of the pixel regions does not overlie the pixel electrode. 4. The active-matrix substrate according to claim 1 , further comprising: a first insulating layer between a gate line layer defining the plurality of gate lines and a data line layer defining the plurality of data lines; one of the control signal lines in one of the pixel regions and in the data line layer that is substantially parallel to the data lines supplies the control signal from a second terminal to the driving circuit; a second insulating layer with a thickness greater than the first insulating layer, located on top of the data line layer, and including a contact hole extending therethrough to the data line layer; and a conductive layer in the contact hole, wherein the one of the control signal lines is interrupted at a location overlying one of the plurality of gate lines, and portions of the one of the control signal lines interrupted are connected via the conductive layer. 5. The active-matrix substrate according to claim 1 , wherein one of the control signal lines in the one of the pixel regions supplies the control signal from a second terminal to the driving circuit; and at least a portion of one of the control signal lines is substantially parallel to the data lines and a same distance from two of the data lines in the one of the pixel regions. 6. The active-matrix substrate according to claim 1 , further comprising: a pixel switching element located in the one of the pixel regions and connected to one of the data lines and one of the gate lines; wherein the one of the gate lines includes a plurality of portions with a width smaller than a maximum width of the one of the gate lines; a first portion of the plurality of portions is between a point on the one of the gate lines to which a gate terminal of the one of the switching elements is connected and a crossing of the one of the data lines and one of the gate lines; and a second portion of the plurality of portions is adjacent to a crossing of a portion of the one of the gate lines to which the gate terminal is not connected and the one of the data lines. 7. The active-matrix substrate according to claim 1 , wherein one of the pixel regions which includes one of the switching elements has a dimension in a direction in which the gate lines extend that is larger than a corresponding dimension of others of the pixel regions. 8. The active-matrix substrate according to claim 1 , wherein the display region includes a plurality of sub-regions arranged in a direction in which the plurality of gate lines is arranged, and a driving circuit of one of the gate lines in each of the plurality of sub-regions applies one of the selection voltage and the non-selection voltage to the one of the gate lines at a frequency that is specified for a corresponding one of the plurality of sub-regions. 9. The active-matrix substrate according to claim 1 , wherein N gate lines (N is a natural number) are provided, a first to M driving circuits (M is a natural number, M≧2) are provided for each of the gate lines, the M driving circuits provided for an nth gate line (1≦n≦N) apply a selection voltage to the nth gate line in an order beginning with the first driving circuit and ending with an Mth driving circuit, a second one of the M driving circuits applies the selection voltage to the nth gate line at a time at which a preceding driving circuit applies the selection voltage to an n+1th gate line, and a first terminal supplies one of the data lines with a data signal for an image to be written to one of the pixel regions defined by the nth gate line and the one of the data lines at a time at which the Mth driving circuit applies the selection voltage to the nth gate line. 10. The active-matrix substrate according to claim 1 , wherein the pixel regions include a plurality of sub-pixel regions, the lines include a plurality of sub-gate lines, a first of the sub-pixel regions includes a first pixel switching element and a first pixel electrode connected to one of the gate lines and one of the data lines via the first pixel switching element, a second of the sub-pixel regions includes a second pixel switching element, a second pixel electrode connected to one of the sub-gate lines and the data line via the second pixel switching element, and a capacitor connected between the second pixel electrode and the first pixel electrode, the driving circuit includes a sub-gate line driver located in one of the pixel regions in which neither the first pixel switching element nor the second pixel switching element is provided, and provided for one of the sub-gate lines to apply one of the selection voltage and the non-selection voltage to the sub-gate line in response to the control signal, and the sub-gate line driver applies the selection voltage to the sub-gate line in one horizontal interval after the selection voltage is applied to the gate line. 11. The active-matrix substrate according to claim 1 , wherein the pixel regions include a plurality of sub-pixel regions, the lines include the gate lines, a plurality of sub-gate lines, and a plurality of auxiliary capacitance lines, each of the plurality of sub-pixel regions includes a pixel electrode connected to one of the gate lines and one of the data lines, one of the plur
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