FFS mode array substrate with TFT channel layer and common electrode layer patterned from a single semiconductor layer and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9798202-B2
Application number	US-201615116229-A
Country	US
Kind code	B2
Filing date	Apr 8, 2016
Priority date	Mar 11, 2016
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

An FFS mode array substrate and a manufacturing method thereof are provided. The FFS mode array substrate has: a glass substrate provided with a gate electrode thereon; a first insulation layer; a semiconductor layer having a channel region and a common electrode region to form a channel semiconductor layer on the channel region of the semiconductor layer, and form a common electrode layer on the common electrode region of the semiconductor layer by doping semiconductor thereon; and a second insulation layer provided with a first through hole and a second through hole therein.

First claim

What is claimed is:

1. A manufacturing method of a FFS (Fringe Field Switching) mode array substrate, comprising steps of:
forming a gate electrode on a glass substrate;
depositing a first insulation layer and a semiconductor layer on the glass substrate and the gate electrode in order, wherein the semiconductor layer has a channel region, a common electrode region, and a third spacing region located between the channel region and the common electrode region;
coating a second photoresist layer on the semiconductor layer, and removing photoresist of the second photoresist layer which corresponds to the third spacing region;
etching the semiconductor layer to form a channel semiconductor layer on the channel region of the semiconductor layer and to form a to-be-doped semiconductor layer on the common electrode region of the semiconductor layer;
removing the second photoresist layer which is on the to-be-doped semiconductor layer, and doping the to-be-doped semiconductor layer to form a common electrode layer;
removing the second photoresist layer which is on the channel semiconductor layer; and
depositing a second insulation layer on the channel semiconductor layer, the common electrode layer and the first insulation layer, and forming a first through hole and a second through hole which are used to expose the channel semiconductor layer.

2. The manufacturing method of the FFS mode array substrate according to claim 1 , further comprising steps of:
depositing a pixel electrode layer on the second insulation layer, wherein the pixel electrode layer has a plurality of pixel electrode regions and first spacing regions located between each two of the pixel electrode regions;
depositing a first metal layer on the pixel electrode layer, wherein the first metal layer has a source electrode region, a drain electrode region, and a second spacing region located between the source electrode region and the drain electrode region;
coating a first photoresist layer on the first metal layer, and removing photoresist of the first photoresist layer which corresponds to the first spacing regions and the second spacing regions;
etching the first metal layer and the pixel electrode layer to respectively form a source electrode and a drain electrode in the source electrode region and the drain electrode region of the first metal layer, and to form a plurality of pixel electrodes in the pixel electrode regions of the pixel electrode layer;
removing the first photoresist layer, and removing the first metal layer which is on the pixel electrodes; and
depositing a third insulation layer on the source electrode, the drain electrode, the pixel electrodes and the second insulation layer.

3. The manufacturing method of the FFS mode array substrate according to claim 2 , wherein two doped regions which respectively correspond to the first through hole and the second through hole are disposed on the channel semiconductor layer, and the step of removing the second photoresist layer which is on the channel semiconductor layer includes: removing the second photoresist layer which is on the two doped regions of the channel semiconductor layer; doping the two doped regions to transform semiconductor of the doped regions into conductors; and then removing the remaining second photoresist layer on the channel semiconductor layer.

4. The manufacturing method of the FFS mode array substrate according to claim 1 , wherein the second insulation layer and the third insulation layer both include silicon nitride or silica.

5. The manufacturing method of the FFS mode array substrate according to claim 1 , wherein the channel semiconductor layer includes indium gallium zinc oxide.

6. The manufacturing method of the FFS mode array substrate according to claim 1 , wherein the pixel electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and a thickness of the pixel electrode layer ranges from 10 nm to 100 nm.

7. A FFS (Fringe Field Switching) mode array substrate, comprising:
a glass substrate having a gate electrode thereon;
a first insulation layer formed on the glass substrate and the gate electrode;
a semiconductor layer formed on the first insulation layer, wherein the semiconductor layer includes a channel region and a common electrode region;
the channel region of the semiconductor layer forms a channel semiconductor layer, and semiconductor of the common electrode region of the semiconductor layer is doped to form a common electrode layer; and
a second insulation layer deposited on the channel semiconductor layer, the common electrode layer and the first insulation layer, wherein a first through hole and a second through hole exposing the channel semiconductor layer are formed in the second insulation layer.

8. The FFS mode array substrate according to claim 7 , which further comprises:
a pixel electrode layer deposited on the second insulation layer, wherein the pixel electrode layer has a plurality of pixel electrodes;
a source electrode and a drain electrode formed on the pixel electrode layer; and
a third insulation layer formed on the source electrode, the drain electrode, the pixel electrodes and the second insulation layer.

9. The FFS mode array substrate according to claim 7 , wherein the channel semiconductor layer includes indium gallium zinc oxide.

10. The FFS mode array substrate according to claim 7 , wherein the pixel electrode layer is an indium tin oxide transparent electrode layer or an indium zinc oxide transparent electrode layer, and a thickness of the pixel electrode layer ranges from 10 nm to 100 nm.

11. A FFS (Fringe Field Switching) mode array substrate, comprising:
a glass substrate having a gate electrode thereon;
a first insulation layer formed on the glass substrate and the gate electrode;
a semiconductor layer formed on the first insulation layer, wherein the semiconductor layer includes a channel region and a common electrode region;
the channel region of the semiconductor layer forms a channel semiconductor layer; and semiconductor of the common electrode region of the semiconductor layer is doped to form a common electrode layer;
a second insulation layer deposited on the channel semiconductor layer, the common electrode layer and the first insulation layer, wherein a first through hole and a second through hole exposing the channel semiconductor layer are formed in the second insulation layer;
a pixel electrode layer deposited on the second insulation layer, wherein the pixel electrode layer has a plurality of pixel electrodes;
a source electrode and a drain electrode formed on the pixel electrode layer; and
a third insulation layer formed on the source electrode, the drain electrode, the pixel electrodes and the second insulation layer;
wherein the second insulation layer and the third insulation layer both include silicon nitride or silica.

Assignees

• Shenzhen China Star Optoelect

Inventors

• Ge Shimin

Classifications

• G02F1/13439 Primary

  characterised by their electrical, optical, physical properties; materials therefor; method of making · CPC title

• H01L29/78606

  Electricity · mapped topic

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• G02F2202/10

  semiconductor · CPC title

• G02F2001/134372

  Physics · mapped topic