Display substrate and manufacturing method thereof, display panel and display device

US9798192B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9798192-B2
Application numberUS-201514785787-A
CountryUS
Kind codeB2
Filing dateMar 27, 2015
Priority dateNov 14, 2014
Publication dateOct 24, 2017
Grant dateOct 24, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display substrate, a manufacturing method thereof, a display panel and a display device are provided. The display substrate includes a display region and a non-display region. A reset zone is provided in the non-display region, and a thickness of a thin film layer provided in the reset zone is smaller than a thickness of a thin film layer provided in a zone adjacent to the reset zone. A step between the thin film layer in the reset zone and the thin film layer in the zone adjacent to the reset zone at the boundary of the reset zone and the zone adjacent to the reset zone is uniform in height; and in a direction within a surface of the display substrate and perpendicular to a rubbing direction of the display substrate, a size of the reset zone is greater than or equal to a size of the display region.

First claim

Opening claim text (preview).

What is claimed is: 1. A display substrate, comprising a display region and a non-display region, wherein, a reset zone is provided in the non-display region, and a thickness of a thin film layer provided in the reset zone is smaller than a thickness of a thin film layer provided in a zone adjacent to the reset zone; a step between the thin film layer in the reset zone and the thin film layer in the zone adjacent to the reset zone at the boundary of the reset zone and the zone adjacent to the reset zone is uniform in height; in a direction within a surface of the display substrate and perpendicular to a rubbing direction of the display substrate, a size of the reset zone is greater than or equal to a size of the display region; and the display substrate is an array substrate, a bonding zone is provided within the reset zone, a protective layer is provided within the reset zone, and the protective layer covers other areas than the bonding zone in the reset zone with exposing a lead wire made of a metallic material within the bonding zone. 2. The display substrate according to claim 1 , wherein, in the case that the lead wire of the bonding zone is formed in a same layer and with a same material as a gate line of the display region, the protective layer comprises a gate insulating layer. 3. The display substrate according to claim 1 , wherein, in the case that an organic thin film layer is provided on a surface of a source/drain metal layer of the array substrate, the organic thin film layer covers other areas than the reset zone. 4. The display substrate according to claim 1 , wherein, the reset zone corresponds to a location of a sealant located on a surface of the array substrate. 5. A display panel, comprising the display substrate according to claim 1 . 6. A display device, comprising the display panel according to claim 5 . 7. A manufacturing method of a display substrate, comprising: forming a display region on a base substrate; and forming a non-display region on the base substrate; wherein, a reset zone is formed in the non-display region, a thickness of a thin film layer provided in the reset zone is smaller than a thickness of a thin film layer provided in a zone adjacent to the reset zone; a step between the thin film layer in the reset zone and the thin film layer in the zone adjacent to the reset zone at the boundary of the reset zone and the zone adjacent to the reset zone is uniform in height; in a direction within a surface of the display substrate and perpendicular to a rubbing direction of the display substrate, a size of the reset zone is greater than or equal to a size of the display region; and the display substrate is an array substrate, a bonding zone is provided within the reset zone, a protective layer is provided within the reset zone, and the protective layer covers other areas than the bonding zone in the reset zone with exposing a lead wire made of a metallic material within the bonding zone. 8. The manufacturing method of the display substrate according to claim 7 , wherein, the method comprises: forming the protective layer in areas other than the bonding zone in the reset zone. 9. The manufacturing method of the display substrate according to claim 7 , wherein, in the case that the lead wire of the bonding zone is formed in a same layer and with a same material as a gate line of the display region, the method comprises: sequentially forming a gate insulating layer, a semiconductor active layer, a source/drain metal layer and a passivation layer on a surface of the lead wire, and coating a photoresist on a surface of the passivation layer; forming a photoresist fully-removed region, a photoresist partially-retained region and a photoresist fully-retained region by using one exposure and development process; wherein, the photoresist fully-removed region corresponds to the bonding zone, the photoresist partially-retained region corresponds to other areas than the bonding zone in the reset zone, and the photoresist fully-retained region corresponds to other areas than the reset zone; etching the passivation layer, the source/drain metal layer, the semiconductor active layer and the gate insulating layer that correspond to the photoresist fully-removed region; removing the photoresist at the photoresist partially-retained region by ashing, and etching the passivation layer, the source/drain metal layer and the semiconductor active layer that correspond to the photoresist partially-retained region; and stripping off the photoresist situated at the photoresist fully-retained region. 10. The manufacturing method of the display substrate according to claim 7 , wherein, in the case that an organic thin film layer is formed between a source/drain metal layer and a passivation layer, the forming the reset zone comprises: by using one patterning process, removing at least the passivation layer and the organic thin film layer provided in the reset zone. 11. The display substrate according to claim 2 , wherein, in the case that an organic thin film layer is provided on a surface of a source/drain metal layer of the array substrate, the organic thin film layer covers other areas than the reset zone. 12. The display substrate according to claim 2 , wherein, the reset zone corresponds to a location of a sealant located on a surface of the array substrate. 13. The display substrate according to claim 3 , wherein, the reset zone corresponds to a location of a sealant located on a surface of the array substrate. 14. The manufacturing method of the display substrate according to claim 8 , wherein, in the case that the lead wire of the bonding zone is formed in a same layer and with a same material as a gate line of the display region, the method comprises: sequentially forming a gate insulating layer, a semiconductor active layer, a source/drain metal layer and a passivation layer on a surface of the lead wire, and coating a photoresist on a surface of the passivation layer; forming a photoresist fully-removed region, a photoresist partially-retained region and a photoresist fully-retained region by using one exposure and development process; wherein, the photoresist fully-removed region corresponds to the bonding zone, the photoresist partially-retained region corresponds to other areas than the bonding zone in the reset zone, and the photoresist fully-retained region corresponds to other areas than the reset zone; etching the passivation layer, the source/drain metal layer, the semiconductor active layer and the gate insulating layer that correspond to the photoresist fully-removed region; removing the photoresist at the photoresist partially-retained region by ashing, and etching the passivation layer, the source/drain metal layer and the semiconductor active layer that correspond to the photoresist partially-retained region; and stripping off the photoresist situated at the photoresist fully-retained region. 15. The manufacturing method of the display substrate according to claim 8 , wherein, in the case that an organic thin film layer is formed between a source/drain metal layer and a passivation layer, the forming the reset zone comprises: by using one patterning process, removing at least the passivation layer and the organic thin film layer provided in the reset zone. 16. The manufacturing method of the display substrate according to claim 9 , wherein, in the case that an organic thin film layer is formed between a source/drain metal layer and a passivation layer, the forming the reset zone comprises: by using one patterning process, removing at least the p

Assignees

Inventors

Classifications

  • Wiring, e.g. gate line, drain line · CPC title

  • Gaskets; Spacers; Sealing of cells · CPC title

  • Colour filters · CPC title

  • Electricity · mapped topic

  • Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence) · CPC title

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What does patent US9798192B2 cover?
A display substrate, a manufacturing method thereof, a display panel and a display device are provided. The display substrate includes a display region and a non-display region. A reset zone is provided in the non-display region, and a thickness of a thin film layer provided in the reset zone is smaller than a thickness of a thin film layer provided in a zone adjacent to the reset zone. A step …
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Hefei Boe Optoelectronics Tech
What technology area does this patent fall under?
Primary CPC classification G02F1/133784. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 24 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).