Test circuit and method of controlling test circuit

Patent metadata

Field	Value
Publication number	US-9797949-B2
Application number	US-201514919105-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Dec 26, 2014
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.

First claim

What is claimed is:

1. A test circuit which is provided to a semiconductor device including a plurality of semiconductor chips, and tests the semiconductor device, comprising:
a test clock terminal which is provided to a first semiconductor chip among the plurality of semiconductor chips, and receives a test clock signal that is used when testing the semiconductor device;
a plurality of first clock paths which are disposed between the first semiconductor chip and a second semiconductor chip among the plurality of semiconductor chips, and through which the test clock signal that is received by the test clock terminal is transmitted from the first semiconductor chip to the second semiconductor chip;
a test circuit which is provided to the second semiconductor chip, and tests the second semiconductor chip by using the test clock signal that is transmitted to the second semiconductor chip;
a first clock detection circuit which is provided to the second semiconductor chip, and detects the test clock signal that is received through at least one of the plurality of first clock paths under a predetermined condition; and
a first clock path selection circuit which is provided to the second semiconductor chip, selects a first clock path, through which the test clock signal detected by the first clock detection circuit is transmitted, among the plurality of first clock paths as a first test clock path, and supplies the test clock signal, which is transmitted through the first test clock path, to the test circuit when the second semiconductor chip is tested.

2. The test circuit according to claim 1 ,
wherein the first clock detection circuit detects the test clock signal, of which a number of clocks reaches a predetermined number for a first time, among a plurality of test clock signals which are received through the plurality of first clock paths, and generates a first clock selection signal that represents the first clock path through which the test clock signal that is detected is transmitted, and
the first clock path selection circuit selects the first clock path, which is represented by the first clock selection signal, among the plurality of first clock paths as the first test clock path.

3. The test circuit according to claim 2 ,
wherein the first clock detection circuit includes,
a plurality of first counters which are respectively provided in correspondence with the plurality of first clock paths, and count a number of clocks of the plurality of test clock signals which are respectively received through the plurality of first clock paths,
a first setting control circuit that asserts, for each of the plurality of first counters, a first control signal when the number of clocks counted by each of the plurality of first counters reaches the predetermined number,
a plurality of first selection signal storages which are respectively provided in correspondence with the plurality of first clock paths, store logical values of the plurality of first control signals, and output the first clock selection signal based on each of the logical values which are stored, and
a first update control circuit that suppresses variation of the logical value of the first clock selection signal after the logical value of the first control signal that is asserted is stored in any one of the plurality of first selection signal storages.

4. The test circuit according to claim 3 ,
wherein the first update control circuit retains a state of the first selection signal storages, other than the one of the plurality of first selection signal storages which stores a logical value of the first control signal that is asserted, to an initial state during a period in which the logical value of the first control signal that is asserted is stored in the one of the plurality of first selection signal storages.

5. The test circuit according to claim 1 , further comprising:
a first switch which is provided to the first semiconductor chip, and is set to any one of a state of transmitting the test clock signal, which is transmitted from the test clock terminal, to the second semiconductor chip, and a state of not transmitting the test clock signal, which is transmitted from the test clock terminal, to the second semiconductor chip.

6. The test circuit according to claim 1 , further comprising:
a test circuit which is provided to the first semiconductor chip, and transmits a first test circuit reset signal that resets the test circuit of the second semiconductor chip, and a first detection circuit reset signal that resets the first clock detection circuit to the second semiconductor chip.

7. The test circuit according to claim 1 , further comprising:
a plurality of second clock paths which are disposed between the second semiconductor chip and a third semiconductor chip among the plurality of semiconductor chips, and transmit the test clock signal, which is transmitted to the second semiconductor chip, to the third semiconductor chip;
a second test circuit which is provided to the third semiconductor chip, and tests the third semiconductor chip by using the test clock signal that is transmitted to the third semiconductor chip;
a second clock detection circuit which is provided to the third semiconductor chip, and detects the test clock signal that is received through each of the plurality of second clock paths; and
a second clock path selection circuit which is provided to the third semiconductor chip, selects a second clock path, through which the test clock signal detected by the second clock detection circuit is transmitted, among the plurality of second clock paths as a second test clock path, and supplies the test clock signal, which is transmitted through the second test clock path, to the second test circuit of the third semiconductor chip when the third semiconductor chip is tested,
wherein the first clock path selection circuit transmits the test clock signal, which is transmitted through the first test clock path, to the third semiconductor chip when the third semiconductor chip is tested.

8. The test circuit according to claim 7 , further comprising:
a second switch, which is provided to the second semiconductor chip and receives the test clock signal transmitted through the first test clock path from the first clock path selection circuit, is set to any one of a state of transmitting the test clock, which is received from the first clock path selection circuit, to the third semiconductor chip, and a state of not transmitting the test clock, which is received from the first clock path selection circuit, to the third semiconductor chip.

9. The test circuit according to claim 7 ,
wherein the test circuit of the second semiconductor chip transmits a second test circuit reset signal that resets the second test circuit of the third semiconductor chip, and a second detection circuit reset signal that resets the second clock detection circuit to the third semiconductor chip.

10. The test circuit according to claim 7 ,
the second clock detection circuit detects the test clock signal, of which a number of clocks reaches a predetermined number for a first time, among a plurality of test clock signals which are received through the plurality of second clock paths, and generates a second clock selection signal that represents the second clock path through which the test clock signal that is detected is transmitted, and
the second clock path selection circuit selects the second clock path, which is represented by the second clock selection signal, among the plurality of second clock paths as the second test clock path.

11. The test circuit according to claim 10 ,
wherein the second clock detection circuit includes,
a plur

Assignees

• Fujitsu Ltd

Inventors

• Oshiyama Gen
• Moriyama Osamu
• Shikibu Takahiro
• Chiyonobu Akihiro
• Yamazaki Iwao

Classifications

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R31/318513 Primary

  Test of Multi-Chip-Moduls · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title