Direct bond transfer layers for manufacturable sealing of microfluidic chips

Patent metadata

Field	Value
Publication number	US-9795964-B2
Application number	US-201514947745-A
Country	US
Kind code	B2
Filing date	Nov 20, 2015
Priority date	Nov 20, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

Techniques for use of wafer bonding techniques for sealing of microfluidic chips are provided. In one aspect, a wafer bonding sealing method includes the steps of: forming a first oxide layer coating surfaces of a first wafer, the first wafer having at least one fluidic chip; forming a second oxide layer on a second wafer; and bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer. The second wafer can be at least partially removed after performing the bonding, and fluidic ports may be formed in the second oxide layer. A fluidic chip device is also provided.

First claim

What is claimed is:

1. A wafer bonding sealing method, comprising the steps of:
forming a first oxide layer coating surfaces of a first wafer, the first wafer comprising at least one fluidic chip having fluidic channels joined by nanochannel structures, wherein each of the nanochannel structures comprises an arrangement of pillars for particle sorting, and wherein the first oxide layer is formed conformally on top and sidewall surfaces of each of the pillars;
forming a second oxide layer on a second wafer; and
bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer.

2. The method of claim 1 , wherein the first oxide layer has a thickness of from about 5 nm to about 50 nm, and ranges therebetween.

3. The method of claim 1 , wherein the second oxide layer has a thickness of from about 0.5 μm to about 2 μm, and ranges therebetween.

4. The method of claim 1 , further comprising the step of:
at least partially removing the second wafer after performing the bonding.

5. The method of claim 1 , further comprising the step of:
fully removing the second wafer after performing the bonding.

6. The method of claim 1 , further comprising the step of:
forming fluidic ports in the second oxide layer over ends of the fluidic channels.

7. The method of claim 6 , wherein the fluidic ports are partially formed through the second oxide layer, the method further comprising the step of:
etching each of the fluidic ports partway through the second oxide layer so as to leave a portion of the second oxide layer separating the fluid ports from the fluidic channels.

8. The method of claim 7 , further comprising the step of:
fully opening the partially formed fluidic ports just prior to use by way of a microfluidic jig comprising needles for piercing the portion of the second oxide layer separating the fluid ports from the fluidic channels.

9. The method of claim 6 , further comprising the steps of:
applying pieces of an adhesive tape selectively to local portions of the second oxide layer where the fluidic ports are to be formed; and
peeling off the pieces of the adhesive tape just prior to use to locally remove portions of the second oxide layer forming the fluidic ports.

10. The method of claim 1 , wherein the step of bonding the first wafer to the second wafer comprises the step of:
annealing the first wafer and the second wafer at a temperature of from about 800° C. to about 1,000° C., and ranges therebetween, for a duration of from about 40 minutes to about 60 minutes, and ranges therebetween, to enforce bonding quality.

11. The method of claim 10 , wherein the annealing is performed in a nitrogen ambient.

12. The method of claim 1 , wherein at least one of the first oxide layer and the second oxide layer comprises a thermal oxide.

13. The method of claim 7 , wherein the portion of the second oxide layer left separating the fluid ports from the fluidic channels has a thickness of from about 50 nm to about 300 nm, and ranges therebetween.

Assignees

• IBM

Inventors

• Smith Joshua T
• Tsang Cornelia K
• Wang Chao
• Wunsch Benjamin H

Classifications

• G01N2015/0288

  Sorting the particles · CPC title

• G01N15/0255

  with mechanical, e.g. inertial, classification, and investigation of sorted collections (with centrifuges G01N15/042) · CPC title

• B01L2400/086

  using baffles or other fixed flow obstructions · CPC title

• B01L2200/0652

  Sorting or classification of particles or molecules · CPC title

• B01L2300/0896

  Nanoscaled · CPC title