Architectures for an implantable medical device system having daisy-chained electrode-driver integrated circuits

US9795793B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9795793-B2
Application numberUS-201113253552-A
CountryUS
Kind codeB2
Filing dateOct 5, 2011
Priority dateOct 13, 2010
Publication dateOct 24, 2017
Grant dateOct 24, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Architectures for an implantable neurostimulator system having a plurality of electrode-driver integrated circuits (ICs) in provided. Electrodes from either or both ICs can be chosen to provide stimulation, and one of the IC acts as the master while the other acts as the slave. A parallel bus operating in accordance with a communication protocol couples the ICs, and certain functional blocks not needed in the slave are disabled. Stimulation parameters are loaded via the bus into each IC, and a stimulation enable command is issued on the bus to ensure simultaneous stimulation from the electrodes on both ICs. Clocking strategies are also disclosed to allow clocking of the master and slave ICs to be independently controlled, and to ensure that relevant internal and bus clocks used in the system are synchronized.

First claim

Opening claim text (preview).

What is claimed is: 1. An implantable stimulator device comprising a plurality of first electrodes and a plurality of second electrodes configured to provide stimulation to a patient's tissue, comprising: a first integrated circuit comprising a first stimulation circuitry block configured to provide a stimulation current to only the plurality of first electrodes; a second integrated circuit identical to the first integrated circuit comprising a second stimulation circuitry block configured to provide a stimulation current to only the plurality of second electrodes; and a conductive case for housing the first and second integrated circuits; wherein each of the first and second electrodes are operable as either an anode or a cathode, wherein any of the first electrodes is selectable to operate as an anode or as cathode, and wherein any of the second electrodes is selectable to simultaneously operate as the other of the anode or cathode, to pass a stimulation current from the anode to the cathode, wherein the first or second integrated circuit is configured to operate as a master integrated circuit, and wherein the other of the first or second integrated circuit is configured to operate as a slave integrated circuit to the master integrated circuit, and wherein bond programming of the first and second integrated circuits is used to configured the first or second integrated circuit as the master integrated circuit, and the other of the first or second integrated circuit as the slave integrated circuit, wherein one or more circuit blocks in the master integrated circuit are enabled while those one or more circuit blocks are disabled in the slave integrated circuit. 2. The device of claim 1 , further comprising: a microcontroller; and a bus in communication with the first and second stimulation circuitry blocks and the microcontroller, wherein the microcontroller selects the anode and the cathode via the bus. 3. The device of claim 2 , wherein the bus comprises a first chip select signal for the first integrated circuit and a second chip select signal for the second integrated circuit. 4. The device of claim 1 , wherein one of the first electrodes or one of the second electrodes comprises the case. 5. The device of claim 1 , wherein the first stimulation circuitry block comprises first digital-to-analog converter circuitry configured to provide the stimulation current to only the plurality of first electrodes, and wherein the second-stimulation circuitry block comprises second digital-to-analog converter circuitry configured to provide the stimulation current to only the plurality of second electrodes. 6. The device of claim 5 , wherein the first digital-to-analog converter circuitry is configured to provide the stimulation current to only the plurality of first electrodes by setting the stimulation current at only the plurality of first electrodes, and wherein the second digital-to-analog converter circuitry is configured to provide the stimulation current to only the plurality of second electrodes by setting the stimulation current at only the plurality of second electrodes. 7. The device of claim 1 , further comprising one or more electrode arrays coupled to lead connectors fixed in a non-conductive header material, wherein the at least one electrode array contains the first and second electrodes. 8. An implantable stimulator device comprising a plurality of first electrodes and a plurality of second electrodes configured to provide stimulation to a patient's tissue, comprising: a first integrated circuit comprising a first stimulation circuitry block configured to provide a stimulation current to only the plurality of first electrodes; a second integrated circuit identical to the first integrated circuit comprising a second stimulation circuitry block configured to provide a stimulation current to only the plurality of second electrodes; and a conductive case for housing the first and second integrated circuits; wherein the first and second integrated circuits are configured to receive a stimulation enable command to cause the first and second stimulation circuitry blocks to simultaneously provide a stimulation current to at least one of the first electrodes and at least one of the second electrodes. 9. The device of claim 8 , further comprising: a microcontroller; and a bus in communication with the first and second stimulation circuitry blocks and the microcontroller, wherein the microcontroller is configured to issue the stimulation enable command on the bus. 10. The device of claim 9 , wherein the bus comprises a parallel bus, and wherein the stimulation enable command comprises a multi-bit command. 11. The device of claim 9 , wherein the stimulation enable command is received at an address register at both the first integrated circuit and the second integrated circuit. 12. The device of claim 9 , wherein the bus comprises a first chip select signal for the first integrated circuit and a second chip select signal for the second integrated circuit. 13. The device of claim 12 , wherein the microcontroller is configured to issue the stimulation enable command with both the first and second chip select signals asserted. 14. The device of claim 8 , wherein one of the first electrodes or one of the second electrodes comprises the case. 15. The device of claim 8 , wherein the first stimulation circuitry block comprises first digital-to-analog converter circuitry configured to provide the stimulation current to the at least one first electrode, and wherein the second stimulation circuitry block comprises second digital-to-analog converter circuitry configured to provide the stimulation current to the at least one second electrode. 16. The device of claim 8 , wherein the first or second integrated circuit is configured to operate as a master integrated circuit, and wherein the other of the first or second integrated circuit is configured to operate as a slave integrated circuit to the master integrated circuit. 17. The device of claim 15 , wherein the first digital-to-analog converter circuitry is configured to provide the stimulation current to the at least one first electrode by setting the stimulation current at the at least one first electrode, and wherein the second digital-to-analog converter circuitry is configured to provide the stimulation current to the at least one second electrode by setting the stimulation current at the at least one second electrode. 18. The device of claim 8 , further comprising one or more electrode arrays coupled to lead connectors fixed in a non-conductive header material, wherein the at least one electrode array contains the first and second electrodes. 19. An implantable stimulator device comprising a plurality of first electrodes and a plurality of second electrodes configured to provide stimulation to a patient's tissue, comprising: a first integrated circuit comprising a first stimulation circuitry block configured to provide a stimulation current to only the plurality of first electrodes; a second integrated circuit identical to the first integrated circuit comprising a second stimulation circuitry block configured to provide a stimulation current to only the plurality of second electrodes; and a conductive case for housing the first and second integrated circuits; wherein each of the first and second electrodes are operable as either an anode or a cathode, wherein any of the first electrodes is selectable to operate as an anode or as cathode, and wherein any of the second electrodes is sel

Assignees

Inventors

Classifications

  • A61N1/372Primary

    Arrangements in connection with the implantation of stimulators · CPC title

  • Digital circuitry features of electrotherapy devices, e.g. memory, clocks, processors · CPC title

  • Details of circuitry or electric components · CPC title

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What does patent US9795793B2 cover?
Architectures for an implantable neurostimulator system having a plurality of electrode-driver integrated circuits (ICs) in provided. Electrodes from either or both ICs can be chosen to provide stimulation, and one of the IC acts as the master while the other acts as the slave. A parallel bus operating in accordance with a communication protocol couples the ICs, and certain functional blocks no…
Who is the assignee on this patent?
Parramon Jordi, Feldman Emanuel, Griffith Paul J, and 2 more
What technology area does this patent fall under?
Primary CPC classification A61N1/372. Mapped technology areas include Human Necessities.
When was this patent published?
Publication date Tue Oct 24 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).