Semiconductor device

US9795049B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9795049-B2
Application numberUS-201514626569-A
CountryUS
Kind codeB2
Filing dateFeb 19, 2015
Priority dateAug 22, 2014
Publication dateOct 17, 2017
Grant dateOct 17, 2017

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a base plate, a semiconductor chip, and a first to a fourth terminal plates. The first terminal plate includes a first main body unit. The second terminal plate includes a second main body unit. The second main body unit opposes the first main body unit. The third terminal plate includes a third main body unit. The third main body unit opposes the first main body unit and the second main body unit. The fourth terminal plate includes a fourth main body unit. The fourth main body unit opposes the third main body unit. A thickness of the third main body unit is thinner than a thickness of the first main body unit. A thickness of the fourth main body unit is thinner than a thickness of the second main body unit.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a base plate having a support surface; a semiconductor chip provided on the support surface, the semiconductor chip including a switching element, the switching element including a first electrode, a second electrode, and a control electrode; a first terminal plate including a first main body unit, the first terminal plate being electrically connected to the first electrode; a second terminal plate including a second main body unit, the second main body unit opposing the first main body unit at a first spacing from the first main body unit, the second terminal plate being electrically connected to the second electrode; a third terminal plate including a third main body unit, the third main body unit opposing the first main body unit and the second main body unit at prescribed spacings from the first main body unit and the second main body unit, the third terminal plate being electrically connected to the first electrode and the first terminal plate; and a fourth terminal plate including a fourth main body unit, the fourth main body unit opposing the third main body unit at a second spacing from the third main body unit, the fourth terminal plate being electrically connected to the second electrode and the second terminal plate, the second spacing being narrower than the first spacing. 2. The device according to claim 1 , further comprising a case provided on the support surface, the case being insulative, the case covering the semiconductor chip, the first main body unit, the second main body unit, the third main body unit, and the fourth main body unit, the first main body unit, the second main body unit, the third main body unit, and the fourth main body unit extending in a perpendicular direction perpendicular to the support surface, a first terminal plate including a first terminal unit, the first terminal unit being provided at one end in the perpendicular direction of the first main body unit to protrude outside the case, and a second terminal plate including a second terminal unit, the second terminal unit being provided at one end in the perpendicular direction of the second main body unit to protrude outside the case. 3. The device according to claim 1 , further comprising a substrate provided on the support surface, the substrate including a substrate main body, a first interconnect pattern, and a second interconnect pattern, the substrate main body being insulative, the first interconnect pattern being provided on the substrate main body, the second interconnect pattern being provided to be separated from the first interconnect pattern on the substrate main body, the semiconductor chip being provided on the first interconnect pattern of the substrate, the first electrode being electrically connected to the first interconnect pattern, the second electrode being electrically connected to the second interconnect pattern, the first terminal plate and the third terminal plate being electrically connected to the first electrode via the first interconnect pattern, the second terminal plate and the fourth terminal plate being electrically connected to the second electrode via the second interconnect pattern. 4. The device according to claim 3 , wherein a plurality of the substrates and a plurality of the semiconductor chips are provided, the substrates are provided to be arranged in a first direction on the support surface, each of the semiconductor chips is provided on each of the first interconnect patterns of each of the substrates, the first electrodes of the semiconductor chips are electrically connected to the first interconnect patterns, the second electrodes of the semiconductor chips are electrically connected to the second interconnect patterns, the first main body unit, the second main body unit, the third main body unit, and the fourth main body unit extend in the first direction, the first terminal plate and the third terminal plate are electrically connected to each of the first interconnect patterns, and the second terminal plate and the fourth terminal plate are electrically connected to each of the second interconnect patterns. 5. The device according to claim 1 , further comprising an insulating member provided between the third main body unit and the fourth main body unit, a plurality of the third terminal plates, a plurality of the fourth terminal plates, and a plurality of the insulating members being provided, and stacked bodies being arranged with a spacing between the stacked bodies, each of the stacked bodies including the third terminal plate, the fourth terminal plate, and the insulating member. 6. The device according to claim 1 , further comprising an insulating member provided between the third main body unit and the fourth main body unit, a plurality of the third terminal plates, a plurality of the fourth terminal plates, and a plurality of the insulating members being provided, and the third terminal plates and the fourth terminal plates being stacked alternately with the insulating members interposed. 7. The device according to claim 1 , wherein the first terminal plate includes a first connector electrically connected to the first electrode, the second terminal plate includes a second connector electrically connected to the second electrode, the third terminal plate includes a third connector and a bend portion, the third connector is electrically connected to the first electrode, the bend portion of the third terminal plate is provided between the third main body unit and the third connector, and the fourth terminal plate includes a fourth connector and a bend portion, the fourth connector is electrically connected to the second electrode, the bend portion of the fourth terminal plate is provided between the fourth main body unit and the fourth connector. 8. The device according to claim 7 , wherein the third main body unit and the fourth main body unit extend in one direction parallel to the support surface, and the bend portion of the third terminal plate and the bend portion of the fourth terminal plate are bent around an axis in the one direction. 9. The device according to claim 1 , wherein the first terminal plate includes a first connector and a bend portion, the first connector is electrically connected to the first electrode, the bend portion of the first terminal plate is provided between the first main body unit and the first connector, and the second terminal plate includes a second connector and a bend portion, the second connector is electrically connected to the second electrode, a bend portion of the second terminal plate is provided between the second main body unit and the second connector. 10. The device according to claim 9 , wherein the first main body unit and the second main body unit extend in one direction parallel to the support surface, and the bend portion of the first terminal plate and the bend portion of the second terminal plate are bent around an axis in one other direction parallel to the support surface and perpendicular to the one direction. 11. The device according to claim 1 , wherein the third main body unit has a plurality of openings, and the fourth main body unit has a plurality of openings. 12. The device according to claim 11 , wherein the openings are arranged in two-dimensional matrix configurations, and the third main body unit and the fourth main body unit have mesh configurations. 13. The device according to claim 1 , wherein the thickness of the third main body unit is not less than 0.01 times and not more than 0.1 times the thickness of the first main

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • specially adapted for the configuration of power bus bars · CPC title

  • H05K7/1432Primary

    specially adapted for power drive units or power converters · CPC title

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Frequently asked questions

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What does patent US9795049B2 cover?
A semiconductor device includes a base plate, a semiconductor chip, and a first to a fourth terminal plates. The first terminal plate includes a first main body unit. The second terminal plate includes a second main body unit. The second main body unit opposes the first main body unit. The third terminal plate includes a third main body unit. The third main body unit opposes the first main body…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H05K7/14329. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 17 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).