Data on clock lane of source synchronous links

Patent metadata

Field	Value
Publication number	US-9794054-B2
Application number	US-201514788721-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Jun 30, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.

First claim

The invention claimed is:

1. A source synchronous data transferring device comprising:
a data transmitting device including:
a clock signal generator that generates a clock signal;
a data source;
a first driver coupled to the data source and to an output of the clock signal generator, the first driver configured to receive first data from the data source and to output a modulated clock signal that is based on the clock signal and encodes the first data into the modulated clock signal by modulating an absolute value of an amplitude of the clock signal based on a value of the first data, the first driver modulates the amplitude of the clock signal between a first threshold value and a second threshold value, the first and second threshold values representing respective data values of the first data;
a clock output coupled to the first driver that provides the modulated clock signal; and
a second driver coupled to the data source and configured to receive second data from the data source, the second driver having a data output that outputs the second data, the clock output and the data output being separate outputs.

2. The source synchronous data transferring device of claim 1 wherein both a rising edge and a falling edge of a clock cycle of the modulated clock signal indicate individual bits of the first data.

3. The source synchronous data transferring device of claim 1 wherein the clock signal generator is a clock multiplier.

4. The source synchronous data transferring device of claim 1 wherein the clock signal generator is clock buffer.

5. A source synchronous data transferring device comprising:
a clock signal generator that generates a clock signal;
a first driver coupled to the output of the clock signal generator and receives the clock signal, the first driver outputs a modulated clock signal that is based on the clock signal and encodes first data into the modulated clock signal by modulating an absolute value of an amplitude of the clock signal based on a value of the first data; and
a clock output coupled to the first driver that provides the modulated clock signal,
wherein the first driver modulates the amplitude of the clock signal between a first threshold value and a second threshold value, wherein the first and second threshold values each represent respective data values of the first data.

6. The source synchronous data transferring device of claim 5 comprising a second driver having a data output that outputs second data.

7. The source synchronous data transferring device of claim 6 comprising a data source coupled to the first and second drivers, wherein the first and second data are retrieved from the data source.

8. A source synchronous data transferring device comprising:
a clock signal generator that generates a clock signal;
a first driver coupled to the output of the clock signal generator and that receives the clock signal, the first driver outputs a modulated clock signal that is based on the clock signal and encodes first data into the modulated clock signal by modulating an absolute value of an amplitude of the clock signal based on a value of the first data; and
a clock output coupled to the first driver that provides the modulated clock signal,
wherein the first driver modulates the amplitude of the clock signal between at least four different threshold values, each threshold value representing a respective data value of the first data.

9. The source synchronous data transferring device of claim 8 comprising a second driver having a data output that outputs second data.

10. The source synchronous data transferring device of claim 9 comprising a data source coupled to the first and second drivers, wherein the first and second data are retrieved from the data source.

11. A method comprising:
generating a first clock signal in a data transmitting device;
receiving, by a first driver in the data transmitting device, first data from a data source in the data transmitting device;
generating a modulated clock signal, by the first driver, and encoding the first data in the modulated clock signal by modulating an absolute value of an amplitude of the first clock signal between a first threshold value and a second threshold value, the first and second threshold values representing respective data values of the first data;
outputting the modulated clock signal from a clock output of the data transmitting device;
receiving, by a second driver in the data transmitting device, second data from the data source in the data transmitting device; and
outputting a data signal from a data output of the second driver in the data transmitting device, the data signal including the second data, the clock output and the data output being separate outputs.

12. The method of claim 11 comprising:
providing the modulated clock signal to a comparator of a data receiving device; and
outputting a normalized clock signal from the comparator, the normalized clock signal having a constant amplitude and a same frequency as the modulated clock signal.

13. A method comprising:
generating a first clock signal in a data transmitting device;
generating a modulated clock signal in the data transmitting device based on the first clock signal;
encoding first data in the modulated clock signal by modulating an absolute value of an amplitude of the first clock signal;
outputting the modulated clock signal from a clock output of the data transmitting device;
outputting a data signal from a data output of the data transmitting device, the data signal including second data;
receiving in a clock input of a data receiving device the modulated clock signal from the clock output;
retrieving in the data receiving device the first data from the modulated clock signal;
receiving in a data input of the data receiving device the data signal; and
retrieving in the data receiving device the second data from the data signal.

14. The method of claim 13 comprising:
providing the modulated clock signal to a comparator of the data receiving device; and
outputting a normalized clock signal from the comparator, the normalized clock signal having a constant amplitude and a same frequency as the modulated clock signal.

15. The method of claim 14 comprising:
providing the normalized clock signal to respective clock inputs of a plurality of flip-flops of the data receiving device;
providing the data signal, or a processed data signal derived from the data signal, to a first flip-flop of the plurality of flip-flops;
providing the modulated clock signal, or a processed clock data signal derived from the modulated clock signal, to a second flip-flop of the plurality of flip-flops; and
retrieving the first and second data from the first and second flip-flops, respectively.

16. The method of claim 15 comprising:
generating the processed data signal by supplying the first signal to a second comparator; and
generating the processed clock data signal by passing the modulated clock signal to a differential difference amplifier.

17. A system comprising:
a data transfer device including:
a clock signal generator configured to generate a clock signal;
a driver configured to receive the clock signal and to generate a modulated clock signal based on the clock signal;
a clock output coupled to the driver and configured to output the modulated clock signal; and
a data output configured to output a data signal;

a data receiving device comprising:
a clock input coupled to the clock output of the data transfer device and configured to receive the modulated clock

Assignees

• St Microelectronics Int Nv

Inventors

• Nandy Tapas
• Gupta Nitin

Classifications

• G06F13/4252

  using a handshaking protocol · CPC title

• H04L5/00

  Arrangements affording multiple use of the transmission path · CPC title

• G06F13/4208 Primary

  being a system bus, e.g. VME bus, Futurebus, Multibus · CPC title

• H04L7/0008 Primary

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• H04J3/0685

  Clock or time synchronisation in a node; Intranode synchronisation · CPC title