High speed and high voltage driver

Patent metadata

Field	Value
Publication number	US-9793892-B2
Application number	US-201615066647-A
Country	US
Kind code	B2
Filing date	Mar 10, 2016
Priority date	Mar 10, 2016
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Systems, methods, and apparatus for biasing a high speed and high voltage driver using only low voltage transistors are described. The apparatus and method are adapted to control biasing voltages to the low voltage transistors such as not to exceed operating voltages of the low voltage transistors while allowing for DC to high speed operation of the driver at high voltage. A stackable and modular architecture of the driver and biasing stages is provided which can grow with a higher voltage requirement of the driver. Capacitive voltage division is used for high speed bias voltage regulation during transient phases of the driver, and resistive voltage division is used to provide bias voltage at steady state. A simpler open-drain configuration is also presented which can be used in pull-up or pull-down modes.

First claim

The invention claimed is:

1. A high speed high voltage (HSHV) driver comprising:
a first stack of transistors of a first type coupled between a high voltage and an output node of the HSHV driver;
a second stack of transistors of a second type opposite the first type coupled between the output node and a reference voltage;
a first biasing circuit configured to provide biasing voltages to the first stack, the first biasing circuit comprising a first biasing stack of transistors of the second type; and
a second biasing circuit configured to provide biasing voltages to the second stack, the second biasing circuit comprising a second biasing stack of transistors of the first type,
wherein:
the HSHV driver operates as an inverter with an input signal having a low voltage and an output signal at the output node having the high voltage,
transistors of the first stack, the second stack, the first biasing stack and the second biasing stack having desired operating voltages substantially smaller than the high voltage,
transistors of each of the first stack, the first biasing stack, the second stack and the second biasing stack are coupled in series with common source-drain nodes, forming a sequence of coupled transistors with a first transistor and a last transistor,
a gate node of the first transistor of the first stack is configured to receive a level shifted version of the input signal,
a gate node of the first transistor of the second stack is configured to receive the input signal,
a source node of the first transistor of the first stack is coupled to the high voltage;
a source node of the first transistor of the second stack is coupled to the reference voltage;
a drain node of the last transistor of the first stack and a drain node of the last transistor of the second stack are coupled to the output node;
gate nodes of a first to a last transistor of the first stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the first biasing stack,
common source-drain nodes of the first to the last transistor of the first stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the first biasing stack,
gate nodes of a first to a last transistor of the second stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the second biasing stack,
common source-drain nodes of the first to the last transistor of the second stack are coupled sequentially and in a one to one relationship to gate nodes of the first to the last transistor of the second biasing stack,
the first biasing circuit further comprises a plurality of series connected resistors configured as a first resistive voltage divider between the high voltage coupled to the source node of the first transistor of the first stack and the output node coupled to the drain node of the last transistor of the first stack, where resistive nodes of the first resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the common source-drain nodes of the transistors of the first stack in a one to one relationship, and
the second biasing circuit further comprises a plurality of series connected resistors configured as a second resistive voltage divider between the reference voltage coupled to the source node of the first transistor of the second stack and the output node coupled to the drain node of the last transistor of the second stack, where resistive nodes of the second resistive voltage divider connecting two consecutive resistors of the plurality of series connected resistors are coupled to the common source-drain nodes of the transistors of the second stack in a one to one relationship.

2. The HSHV driver of claim 1 , wherein the HSHV driver operates in:
an ON mode, wherein a voltage at the output node of the HSHV driver is substantially equal to the high voltage, and
an OFF mode, wherein the voltage at the output node of the HSHV driver is substantially equal to the reference voltage,
wherein operation in one of the ON mode and the OFF mode is based on a voltage level of the input signal to the HSHV driver.

3. The HSHV driver of claim 2 , wherein in the ON mode, all transistors of the first stack and the first biasing stack are ON and all transistors of the second stack and second biasing stack are OFF, and in the OFF mode, all transistors of the first stack and the first biasing stack are OFF and all transistors of the second stack and second biasing stack are ON.

4. The HSHV driver of claim 1 , wherein the first stack or second stack comprise a number of stacked transistors equal to or higher than three.

5. The HSHV driver of claim 1 , wherein the first type is P-type and the second type is N-type.

6. The HSHV driver of claim 1 , wherein:
the input signal is configured to switch between the reference voltage and a voltage higher than the reference voltage, and
the level shifted version of the input signal is equal to the sum of the input signal and a DC voltage substantially equal to the high voltage minus the voltage higher than the reference voltage.

7. The HSHV driver of claim 6 , wherein the voltage higher than the reference voltage is not greater than each of the desired operating voltages.

8. The HSHV driver of claim 1 , wherein the biasing voltages to the first and the second stacks are provided by coupling of the first biasing circuit and the second biasing circuit to the gate nodes and common source-drain nodes of the first stack and the second stack, respectively.

9. The HSHV driver of claim 8 , wherein a transition of the first stack between an ON mode and an OFF mode comprises a sequential turning ON of the first transistor to the last transistor of the second stack responsive to the biasing voltages to the second stack, in synchrony with a sequential turning OFF of the first transistor to the last transistor of the first stack responsive to the biasing voltages to the first stack.

10. The HSHV driver of claim 8 , wherein a transition of the first stack between an OFF mode and an ON mode comprises a sequential turning ON of the first transistor to the last transistor of the first stack responsive to the biasing voltages to the first stack, in synchrony with a sequential turning OFF of the first transistor to the last transistor of the second stack responsive to the biasing voltages to the second stack.

11. The HSHV driver of claim 1 , wherein the coupling from the resistive nodes of the resistive voltage dividers to the common source-drain nodes is one or more of a) a direct coupling, b) a resistive coupling, and c) a transistor coupling.

12. The HSHV driver of claim 1 , comprising:
coupling from the resistor nodes to the gate nodes of the first and second transistor stacks.

13. The HSHV driver of claim 12 , wherein the coupling comprises a transistor arranged as a source-follower circuit.

14. The HSHV driver of claim 12 , wherein:
the first biasing circuit further comprises a plurality of capacitors coupled between the resistive node of the first resistive voltage divider and the high voltage, and
the second biasing circuit further comprises a plurality of capacitors coupled between the resistive node of the second resistive voltage divider and the reference voltage.

15. The HSHV driver of claim 14 , wherein:
each of the plurality of capacitors of the first biasing circuit is connected between a resistive node of the first resistive voltage divider and the high voltage, and

Assignees

• Peregrine Semiconductor Corp

Inventors

• Wu Gary Chunshien

Classifications

• H03K2217/0081

  Power supply means, e.g. to the switch driver · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H03K19/017509

  Interface arrangements · CPC title

• H03K17/102

  in field-effect transistor switches · CPC title

• H03K17/6872 Primary

  using complementary field-effect transistors · CPC title