System and method for a switch transistor driver

Patent metadata

Field	Value
Publication number	US-9793890-B2
Application number	US-201514706593-A
Country	US
Kind code	B2
Filing date	May 7, 2015
Priority date	May 7, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

In accordance with an embodiment, a method of driving a switching transistor includes receiving an activation signal for the switching transistor and generating a sequence of random values. Upon receipt of the activation signal, a control node of the switching transistor is driven with a drive strength based on a random value of the sequence of random values.

First claim

What is claimed is:

1. A method of driving a switching transistor, the method comprising:
receiving an activation signal for the switching transistor;
generating a sequence of random values; and
upon receipt of the activation signal, driving a control node of the switching transistor with a drive strength based on a random value of the sequence of random values.

2. The method of claim 1 , wherein:
driving the control node of the switching transistor comprises driving the control node of the switching transistor with a driver circuit; and
the method further comprises adjusting the driver circuit according to the random value of the sequence of random values.

3. The method of claim 2 , wherein adjusting the driver circuit comprises adjusting an output impedance of the driver circuit.

4. The method of claim 3 , wherein adjusting the output impedance of the driver circuit comprises selectively activating a subset of a plurality of parallel output drivers, wherein a number of output drivers in the subset is based on the random value of the sequence of random values.

5. The method of claim 4 , wherein selectively activating a subset of a plurality parallel output drivers comprises applying the random value to an input of a lookup table and determining the subset of the plurality of parallel output drivers based on an output of the lookup table.

6. The method of claim 2 , wherein adjusting the driver circuit comprises adjusting an output voltage of the driver circuit according to the random value of the sequence of random values.

7. The method according to claim 6 , wherein driving the control node of the switching transistor comprises applying the adjusted output voltage to the control node of the switching transistor via at least one resistor.

8. A method of driving a switching transistor, the method comprising:
receiving an activation signal for the switching transistor;
generating a sequence of random values;
adjusting a driver circuit according to a random value of the sequence of random values; and
upon receipt of the activation signal, driving a control node of the switching transistor with a drive strength based on the random value of the sequence of random values, wherein
driving the control node of the switching transistor comprises driving the control node of the switching transistor with the driver circuit,
adjusting the driver circuit comprises adjusting an output voltage of the driver circuit according to the random value of the sequence of random values, and
adjusting the output voltage comprises applying the random value to an input of a digital-to-analog converter and coupling an output of the digital-to-analog converter to the control node of the switching transistor.

9. The method of claim 2 , wherein adjusting the driver circuit comprises adjusting an output current of the driver circuit.

10. The method of claim 1 , wherein generating the sequence of random values comprises using a linear feedback shift register.

11. The method of claim 1 , wherein driving the control node of the switching transistor with the drive strength based on the random value of the sequence of random values is configured to attenuate peaks in a spectrum of electromagnetic interference (EMI).

12. A circuit comprising:
a random sequence circuit configured to produce a sequence of random values; and
an adjustable drive circuit having an output configured to be coupled to a control node of a switching transistor, the adjustable drive circuit configured to produce a drive signal upon receipt of an activation signal, wherein the drive signal has a drive strength based on a random value of the sequence of random values.

13. The circuit of claim 12 , further comprising the switching transistor coupled to the output of the adjustable drive circuit.

14. The circuit of claim 13 , further comprising a resistor coupled between the output of the adjustable drive circuit and the control node of the switching transistor.

15. The circuit of claim 12 , wherein the random sequence circuit and the adjustable drive circuit are disposed on a semiconductor substrate.

16. The circuit of claim 12 , wherein the adjustable drive circuit has an output impedance based on the random value.

17. The circuit of claim 12 , wherein the adjustable drive circuit has an output voltage based on the random value.

18. The circuit of claim 12 , wherein the adjustable drive circuit has an output current based on the random value.

19. The circuit of claim 12 , wherein
the random sequence circuit comprises a plurality of activation outputs; and
the random sequence circuit configured to determine a subset of the plurality of activation outputs based on the random value and activate the subset of the plurality of activation outputs.

20. The circuit of claim 19 , wherein the adjustable drive circuit comprises a plurality of output drivers having corresponding input coupled to the plurality of activation outputs.

21. The circuit of claim 20 , wherein the plurality of output drivers are coupled in parallel.

22. The circuit of claim 20 , wherein each of the plurality of output drivers comprises a high-side drive and a low-side driver, wherein an output of the high side driver is coupled to an output of the low-side driver.

23. The circuit of claim 12 , wherein the random sequence circuit comprises a linear feedback shift register.

24. An integrated circuit comprising:
a pseudo-random sequence generator;
a plurality of output drivers configured to be coupled to an external switch transistor; and
a logic circuit having inputs coupled to an output of the pseudo-random sequence generator and outputs coupled to the plurality of output drivers, the logic circuit configured to activate a subset of the plurality of output drivers based on an output of the pseudo-random sequence generator upon receipt of an activation signal to modulate a steepness of a switching slope at a control node of the external switch transistor on a cycle by cycle basis.

25. The integrated circuit of claim 24 , wherein the plurality of output drivers are coupled in parallel.

26. The integrated circuit of claim 24 , wherein the each of the plurality of output drivers comprises a high-side drive and a low-side driver, wherein an output of the high side driver is coupled to an output of the low-side driver.

27. The integrated circuit of claim 24 , wherein the pseudo-random sequence generator comprises a linear feedback shift register followed by a lookup table.

28. The method of claim 1 , further comprising upon receipt of the activation signal varying a slew rate of the control node of the switching transistor on a cycle by cycle basis.

29. The circuit of claim 12 , wherein the drive strength of the drive signal changes on a cycle by cycle basis.

30. The method of claim 2 , wherein adjusting the driver circuit comprises adjusting a supply voltage of the driver circuit.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Kirchner Uwe
• Koffler Harald Christian
• Norling Karl

Classifications

• H03K17/167

  using parallel switching arrangements · CPC title

• H03K17/168 Primary

  in composite switches · CPC title

• H03K17/567 Primary

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title