Imager integrated circuit and stereoscopic image capture device

Patent metadata

Field	Value
Publication number	US-9793308-B2
Application number	US-201213432483-A
Country	US
Kind code	B2
Filing date	Mar 28, 2012
Priority date	Apr 22, 2011
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

An imager integrated circuit intended to cooperate with an optical system configured to direct light rays from a scene to an inlet face of the circuit, the circuit being configured to perform a simultaneous stereoscopic capture of N images corresponding to N distinct views of the scene, each of the N images corresponding to light rays directed by a portion of the optical system which is different from those directing the rays corresponding to the N−1 other images, including:
N subsets of pixels made on a same substrate, each of the N subsets of pixels being intended to perform the capture of one of the N associated images, means interposed between each of the N subsets of pixels and the inlet face of the circuit, and configured to pass the rays corresponding to the image associated with said subset of pixels and block the other rays.

First claim

The invention claimed is:

1. An imager integrated circuit intended to cooperate with an optical system configured to direct light rays from a scene to an inlet face of the imager integrated circuit, said imager integrated circuit being configured to perform a simultaneous stereoscopic capture of N images corresponding to N distinct views of the scene, N being an integer higher than 1, each of the N images corresponding to light rays directed by a portion of the optical system which is different from those directing the light rays corresponding to the N−1 other images, the imager integrated circuit including:
N subsets of pixels made on a same substrate, each of the N subsets of pixels being intended to perform the capture of one of the N images associated therewith,
means interposed between each of the N subsets of pixels and the inlet face of the imager integrated circuit, and configured to pass the light rays corresponding to the image associated with said subset of pixels and block the other light rays directed from the optical system to said subset of pixels,
and wherein said means include:
at least two opaque layers superimposed one above the other with a space therebetween, provided between the pixels and the inlet face of the imager integrated circuit, both opaque layers having, passing therethrough, a plurality of holes forming, towards each pixel, at least one pair of superimposed diaphragms, formed by the alignment of the holes in one of the at least two opaque layers being different than the alignment of the holes in another of the at least two opaque layers, configured to pass a part of the light rays corresponding to the image associated with the subset of pixels of which said pixel is part and configured to block other light rays directed from the optical system to said pixel and corresponding to the other images, and
wherein the optical system is facing the two opaque layers, wherein means is configured to
pass light rays to at least one first subset of pixels from a portion of a right half of the optical system,
pass light rays to at least one second subset of pixels from a portion of a left half of the optical system,
block light rays to the at least one first subset of pixels from the portion of the left half of the optical system,
block light rays to the at least one second subset of pixels from the portion of the right half of the optical system, and
pass light rays from a middle point of the optical system to the first and second subsets of pixels,
wherein between the opaque layers and the subsets of pixels, light rays that are not blocked by the opaque layers pass only through a dielectric layer disposed between the opaque layers and the subsets of pixels.

2. The imager integrated circuit according to claim 1 , wherein the number of holes passing through each of both opaque layers is equal to the total number of pixels of the N subsets of pixels.

3. The imager integrated circuit according to claim 1 , wherein, when N equals two and said portion of the optical system corresponds to one half of the optical system, a distance H between the pixels and a second one of both opaque layers, a first of both opaque layers being provided between the pixels and the second one of both opaque layers, is H≦1.5×p·O·n with:
p: pitch of the pixels;
O: numerical aperture of the optical system;
n: optical index of a transparent material provided between both opaque layers.

4. The imager integrated circuit according to claim 1 , wherein the number of holes passing through a first one of both opaque layers is equal to the total number of pixels of the N subsets of pixels, and the number of holes passing through a second one of both opaque layers is equal to (M pix /N)±1, with M pix corresponding to said total number of pixels, said first one of both opaque layers being provided between the pixels and the second one of both opaque layers.

5. The imager integrated circuit according to claim 4 , wherein the distance H between the pixels and the second one of both opaque layers is

H
=

n
·
m
·
O
·

(

N
-
1

)

·
p

(

m
-
1

)

+

(

m
⁢

/

⁢
D

)

·

(

N
-
1

)

·
p

,

with:
D: diameter of the optical system;
D/m: diameter of one of said portions of the optical system;
p: pitch of the pixels;
O: numerical aperture of the optical system;
n: optical index of a transparent material provided between both opaque layers.

6. The imager integrated circuit according to claim 1 , wherein at least one of the opaque layers is formed by electric interconnection lines electrically connected to the pixels.

7. The imager integrated circuit according to claim 1 , wherein the pixels are provided between the inlet face of the imager integrated circuit and electric interconnection lines electrically connected to the pixels.

8. The imager integrated circuit according to claim 1 , wherein holes formed in the opaque layers form side by side aligned trenches or wherein the holes are provided in staggered rows.

9. The imager integrated circuit according to claim 1 , wherein each pixel includes non-photosensitive electric or electronic elements masked by the opaque layers.

10. The imager integrated circuit according to claim 1 , wherein both opaque layers are spaced apart from each other by at least one of the following elements: air, SiO 2 , porous SiO 2 , a resin optically transparent to light rays intended to be captured by the pixels.

11. The imager integrated circuit according to claim 1 , wherein both opaque layers are composed of metal, or resin or metal and resin.

12. The imager integrated circuit according to claim 1 , wherein both opaque layers are covered with at least one antireflection layer.

13. The imager integrated circuit according to claim 1 , wherein the pixels are configured to capture images in the visible region, or in the infrared region, or in both visible and infrared regions.

14. A stereoscopic image capture device including at least one imager integrated circuit according to claim 1 and at least one optical system configured to direct light ra

Assignees

• Gidon Pierre
• Commissariat L Energie Atomique Et Aux Energies Alternatives

Inventors

• Gidon Pierre

Classifications

• H04N23/55

  Optical parts specially adapted for electronic image sensors; Mounting thereof · CPC title

• H04N25/134

  based on three different wavelength filter elements · CPC title

• H04N23/16

  Optical arrangements associated therewith, e.g. for beam-splitting or for colour correction · CPC title

• H04N13/282

  for generating image signals corresponding to three or more geometrical viewpoints, e.g. multi-view systems · CPC title

• H04N13/218

  using spatial multiplexing · CPC title