Semiconductor workpiece with selective backside metallization

Patent metadata

Field	Value
Publication number	US-9793239-B2
Application number	US-201514865816-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Various semiconductor workpieces with selective backside metallizations and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a semiconductor workpiece that has multiple dies. A backside metallization is fabricated on a first die of the dies but not on a second die of the dies.

First claim

What is claimed is:

1. A method of manufacturing, comprising:
providing a semiconductor workpiece having multiple full dies; and
fabricating a backside metallization on a first die of the full dies but not on a second die of the full dies.

2. The method of claim 1 , wherein the backside metallization comprises a unitary structure.

3. The method of claim 1 , wherein the backside metallization comprises a laminate structure.

4. The method of claim 1 , comprising selecting the first die to receive the backside metallization and the second die not to receive the backside metallization based on electrical testing of the first die and the second die.

5. The method of claim 1 , wherein the fabricating the backside metallization comprises applying the backside metallization over the first die and the second die, masking a portion of the backside metallization over the first die while leaving a portion of the backside metallization of the second die exposed and removing the portion of the backside metallization over the second die.

6. The method of claim 1 , wherein the first die dissipates a first power level and the second die dissipates a second power level lower than the first power level.

7. The method of claim 1 , wherein the semiconductor workpiece comprises a wafer.

8. The method of claim 4 , wherein the electrical testing includes testing to determine power dissipation or native clock speed.

9. A method of manufacturing, comprising:
providing a semiconductor workpiece having multiple full dies;
fabricating a backside metallization on a first die of the full dies but not on a second die of the full dies; and
singulating the first die and the second die.

10. The method of claim 9 , comprising mounting the first die on a circuit board.

11. The method of claim 10 , comprising placing a heat spreader in thermal contact with the first die.

12. The method of claim 11 , wherein the heat spreader comprises a lid.

13. The method of claim 9 , comprising mounting the second die on a circuit board.

14. The method of claim 13 , comprising stacking another die on the second die.

15. The method of claim 9 , comprising electrically testing the first die and the second die and selecting the first die to receive the backside metallization and the second die not to receive the backside metallization based on the electrical testing.

16. The method of claim 15 , wherein the electrical testing includes testing to determine power dissipation or native clock speed.

17. The method of claim 9 , wherein the first die dissipates a first power level and the second die dissipates a second power level lower than the first power level.

18. The method of claim 9 , wherein the semiconductor workpiece comprises a wafer.

19. A method of manufacturing, comprising:
providing a semiconductor workpiece having multiple full dies; and
fabricating a first type of backside metallization on a first die of the full dies and a second type of a backside metallization on a second die of the full dies.

20. The method of claim 19 , comprising electrically testing the first die and the second die and selecting the first die to receive the backside metallization and the second die not to receive the backside metallization based on the electrical testing.

21. The method of claim 20 , wherein the electrical testing includes testing to determine power dissipation or native clock speed.

22. The method of claim 19 , wherein the first die dissipates a first power level and the second die dissipates a second power level lower than the first power level.

Assignees

• Su Michael Z
• Alfano Michael S
• Black Bryan
• Advanced Micro Devices Inc

Inventors

• Su Michael Z
• Alfano Michael S
• Black Bryan

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title