Semiconductor device

Patent metadata

Field	Value
Publication number	US-9793196-B2
Application number	US-201615341332-A
Country	US
Kind code	B2
Filing date	Nov 2, 2016
Priority date	Jul 31, 2013
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of transistor units including first, second and third transistor units arranged in a first direction in this order, each transistor unit having a plurality of transistors that are coupled to each other along a second direction intersecting the first direction;
a source wiring having a first portion extending along the second direction, second portions and third portions each extending along the first direction,
wherein the source wiring is shared by first and second transistor units,
wherein the second portions and third portions are connected to the first portion, and
wherein the second portions are coupled to the transistors in the first transistor unit, and the third portions are coupled to the transistors in the second transistor unit;

a drain wiring having a fourth portion extending along the second direction, fifth portions and sixth portions each extending along the first direction,
wherein the drain wiring is shared by second and third transistor units,
wherein the fifth portions and sixth portions are connected to the fourth portion, and
wherein the fifth portions are coupled to the transistors in the second transistor unit, and the sixth portions are coupled to the transistors in the third transistor unit;

a source pad electrode extending in the second direction and overlapping a portion of the first portion via an insulating film, the source pad electrode being coupled to the first portion of the source wiring; and
a drain pad electrode extending in the second direction and overlapping a portion of the fourth portion via the insulating film, the drain pad electrode being coupled to the fourth portion of the drain wiring;
wherein the source pad electrode and the drain pad electrode are arranged in the first direction.

2. The semiconductor device according to claim 1 , wherein:
the first portion is arranged between the first transistor unit and the second transistor unit.

3. The semiconductor device according to claim 2 , wherein:
the fourth portion is arranged between the second transistor unit and the third transistor unit.

4. The semiconductor device according to claim 1 , wherein:
the third portion and the fifth portion are arranged alternately in the second transistor unit along the second direction.

5. The semiconductor device according to claim 1 , further comprising:
source contacts formed on the first portion and arranged in the second direction, wherein the source contacts connect the source wiring with the source pad electrode.

6. The semiconductor device according to claim 5 , further comprising:
drain contacts formed on the fourth portion and arranged in the second direction, wherein the drain contacts connect the drain wiring with the drain pad electrode.

7. The semiconductor device according to claim 1 , further comprising:
a gate pad electrode extending in the second direction; and
a gate plate coupled to the gate pad electrode via a gate contact, the gate plate extending in the first direction.

8. The semiconductor device according to claim 7 , wherein:
the gate plate is coupled to a plurality of gate electrodes via a gate wiring; and
the plurality of gate electrodes have a comb-like shape in the second transistor unit.

9. The semiconductor device according to claim 8 , wherein:
the source pad electrode overlaps at least portions of the plurality of gate electrodes.

10. The semiconductor device according to claim 1 , wherein:
at least part of the source pad electrode overlaps a gate electrode of a plurality of the transistors.

11. The semiconductor device according to claim 1 , wherein:
wherein each of the source and drain pad electrodes has a width in the first direction, which is larger than a width of the respective source and drain wirings, in the first direction.

12. The semiconductor device according to claim 1 , wherein:
a first bonding wire is joined to the source pad electrode, the first bonding wire being coupled to a source terminal of a semiconductor package.

13. The semiconductor device according to claim 12 , wherein:
a second bonding wire is joined to the drain pad electrode, the second bonding wire being coupled to a drain terminal of the semiconductor package.

14. The semiconductor device according to claim 1 , wherein:
bonding wires are joined to the source pad electrode and to the drain pad electrode at a plurality of points, the bonding wires being coupled to a terminal located on a lead frame of a semiconductor package.

15. The semiconductor device according to claim 1 , wherein:
the plurality of transistors are formed on a substrate including a nitride semiconductor layer.

16. The semiconductor device according to claim 15 , wherein:
the nitride semiconductor layer includes GaN and AlGaN.

Assignees

• Renesas Electronics Corp

Inventors

• Matsumoto Akira
• Miura Yoshinao
• Nakashiba Yasutaka

Classifications

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/534

  being rectangular · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title