Soft post package repair of memory devices

Patent metadata

Field	Value
Publication number	US-9793008-B2
Application number	US-201615382394-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Apr 7, 2014
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.

First claim

What is clamed is:

1. A method of operating a memory device that has been packaged and includes a memory array and a first storage element, the method comprising:
entering the memory device into a post package repair mode; and
issuing to the memory device a first activate command with first address data while the memory device is in the post package repair mode, wherein the first activate command causes the memory device to store the first address data in the first storage element as first defective address data and to be free from accessing the memory array responsive to the first address data, and wherein the first defective address data corresponds to a data address of the memory array to be accessed that includes at least one defective memory cell.

2. The method of claim 1 ,
wherein the post package repair mode is a soft post package repair mode and the first storage element comprises a volatile memory.

3. The method of claim 1 ,
wherein the memory device further includes a mode register; and
wherein the entering the memory device into a post package repair mode comprises changing a value stored in the mode register.

4. The method of claim 1 , further comprising:
exiting the memory device from the post package repair mode; and
issuing to the memory device a second activate command with second address data while the memory device is out of the post package repair mode, wherein the second activate command causes the memory device to compare the second address data with the first address data stored in the first storage element to produce a comparison result.

5. The method of claim 4 ,
wherein the memory array comprises a plurality of data addresses and a plurality of redundant addresses; and
wherein the second activate command further causes the memory device to access at least one of the plurality of data addresses when the comparison result indicates that the second address data and the first address data stored in the first storage element do not match and to access at least one of the plurality of redundant addresses when the second address data and the first address data stored in the first storage element match.

6. The method of claim 4 ,
wherein the memory device further includes a second storage element; and
wherein the second activate command further causes the memory device to store the second address data in the second storage element.

7. The method of claim 6 ,
wherein each of the first and second storage elements comprises a volatile memory.

8. A method of operating a memory device that includes a memory array, a first storage element and a programmable element, the method comprising:
storing, before packaging the memory device, first defective address data in the programmable element, wherein the first defective address data corresponds to a first address of the memory array to be accessed that includes at least one defective memory cell;
packaging the memory device;
entering, after the memory device has been packaged, the memory device into a post package repair mode; and
issuing to the memory device a first activate command with first address data while the memory device is in the post package repair mode, wherein the first activate command causes the memory device to store the first address data in the first storage element as second defective address data, wherein the second defective address data corresponds to a second address of the memory array to be accessed that includes at least another detective memory cell, and wherein the first activate command does not cause the memory device to access the memory array responsive to the first address data.

9. The method of claim 8 ,
wherein the post package repair mode is a soft post package repair mode;
wherein the first storage element comprises a volatile memory; and
wherein the programmable element comprises anon-volatile memory.

10. The method of claim 8 ,
wherein the memory device further includes a mode register; and
wherein the entering the memory device into a post package repair mode comprises changing a value stored in the mode register.

11. The method of claim 9 , further comprising:
exiting the memory device from the soft post package repair mode; and
issuing to the memory device a second activate command with second address data while the memory device is out of the post package repair mode, wherein the second activate command causes the memory device to compare the second address data with each of the first and second defective address data to produce a comparison result.

12. The method of claim 11 ,
wherein the second activate command further causes the memory device to access a third address of the memory array when the comparison result indicates that the second address data does not match with each of the first and second defective address data, to access a first redundant address of the memory array when the second address data matches with the first defective address data, and to access a second redundant address of the memory array when the second address data matches with the second defective address data.

13. The method of claim 12 ,
wherein the memory device further includes a second storage element; and
wherein the second activate command further causes the memory device to store the second address data in the second storage element.

14. The method of claim 13 ,
wherein each of the first and second storage elements comprises a volatile memory; and
wherein the programmable element comprises a non-volatile memory.

15. An apparatus comprising:
a controller; and
a memory device coupled to the controller, wherein the memory device comprises a memory array, a non-volatile memory and a volatile memory,
wherein the controller is configured to:
enter the memory device into a soft post package repair mode; and
issue to the memory device a first activate command with first address data while the memory device is in the soft post package repair mode; and
wherein the first activate command causes the memory device to store and hold the first address data in the volatile memory as first defective address data, the first defective address data corresponding to a first address of the memory array to be accessed that includes at least one defective memory cell.

16. The apparatus of claim 15 , wherein the controller is further configured to:
exit the memory device from the soft post package repair mode; and
issue to the memory device a second activate command with second address data while the memory device is out of the soft post package repair mode; and
wherein the second activate command further causes the memory device to compare the second address data with the first defective address data to produce a first comparison output.

17. The apparatus of claim 16 , wherein the second activate command further causes the memory device to access a second address of the memory array when the first comparison output indicates that the second address data and the first defective address data do not match and to access a redundant address of the memory array when the first comparison output indicates that the second address data and the first defective address data match.

18. The apparatus of claim 16 , wherein the non-volatile memory is configured to store second defective address data, the second defective address data corresponding to a second address of the memory array to be accessed that includes at least another defective memory cell; and
wherein the second activate command further causes the memory device to compare the secon

Assignees

• Micron Technology Inc

Inventors

• Wilson Alan J
• Wright Jeffrey

Classifications

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C17/16

  using electrically-fusible links · CPC title