Systems and methods for chip to chip communication

Patent metadata

Field	Value
Publication number	US-9792247-B2
Application number	US-201514801310-A
Country	US
Kind code	B2
Filing date	Jul 16, 2015
Priority date	Jul 18, 2014
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

Systems and methods for chip to chip communication are disclosed. In an exemplary aspect, a chip to chip link comprises a master device having a data transmitter, a clock, a clock transmitter, a phase locked loop (PLL) associated with the clock, and a receiver. The chip to chip link also comprises a slave device that has a data transmitter, a clock receiver, and a data receiver. Noticeably absent from the slave device is a clock or a PLL. By removing the clock from the slave device, the slave device does not have the power consuming element of a slave PLL. Further, because the slave device does not have a clock which would normally have to acquire a new frequency and settle, the master clock may change frequency relatively quickly and vary the frequency across many frequencies, not just one or two predefined frequencies.

First claim

What is claimed is:

1. A master integrated circuit (IC) comprising:
a bus interface configured to be coupled to an interchip bus;
a transmitter comprising a driver, the driver outputting a data signal to the bus interface for transmission across the interchip bus;
a receiver coupled to the bus interface;
a clock data recovery (CDR) circuit operatively coupled to the receiver;
a phase locked loop (PLL) receiving a reference clock signal and outputting a clock signal to the driver of the transmitter and the CDR circuit, wherein the transmitter outputs a master clock signal onto the interchip bus through the bus interface;
a control system operatively coupled to the PLL and the CDR circuit, the control system configured to change a frequency of the master clock signal by controlling the PLL, wherein data transmission continues during frequency change independent of clock activity at a remote slave IC; and
a temperature control circuit operatively coupled to the control system and the CDR circuit, wherein the control system wakes the CDR circuit based on changes in temperature and the temperature control circuit.

2. The master IC of claim 1 , further comprising a timer control circuit operatively coupled to the control system and the CDR circuit, wherein the control system periodically wakes the CDR circuit for a predetermined amount of time based on the timer control circuit to correct for clock drift.

3. The master IC of claim 1 , wherein the temperature control circuit is configured to receive a temperature signal from a temperature sensor.

4. The master IC of claim 1 , wherein the receiver comprises a programmable termination circuit configured to allow variation in a termination impedance associated with the receiver, and wherein the control system configures the termination impedance based on a distance to the remote slave IC.

5. The master IC of claim 1 , further comprising a timer control circuit, wherein the control system is configured to wake the CDR circuit for an amount of time based on the timer control circuit in response to a signal from the temperature control circuit.

6. The master IC of claim 1 , wherein the transmitter further comprises a serializer configured to receive the clock signal from the PLL.

7. The master IC of claim 1 , further comprising a multiplexer coupled to the PLL and configured to receive a low speed clock signal and selectively pass either the clock signal or the low speed clock signal to the transmitter and the CDR circuit.

8. A slave integrated circuit (IC) comprising:
a bus interface configured to be coupled to an interchip bus;
a transmitter comprising a driver, the driver outputting a data signal to the bus interface for transmission across the interchip bus;
a receiver coupled to the bus interface, the receiver configured to extract a clock signal from a signal received from a master IC through the interchip bus;
a clock data recovery (CDR) circuit operatively coupled to the receiver;
a control system operatively coupled to the receiver and the CDR circuit, the control system configured to operate on the clock signal extracted by the receiver without reference to an internal phase locked loop (PLL) or internal clock; and
a temperature control circuit operatively coupled to the control system and the CDR circuit, wherein the control system wakes the CDR circuit based on changes in temperature and the temperature control circuit.

9. The slave IC of claim 8 , further comprising a timer control circuit operatively coupled to the control system and the CDR circuit, wherein the control system periodically wakes the CDR circuit for a predetermined amount of time based on the timer control circuit to correct for clock drift.

10. The slave IC of claim 8 , wherein the temperature control circuit is configured to receive a temperature signal from a temperature sensor.

11. The slave IC of claim 8 , wherein the receiver comprises a programmable termination circuit configured to allow variation in a termination impedance associated with the receiver, and wherein the control system configures the termination impedance based on a distance to the master IC.

12. The slave IC of claim 8 , further comprising a timer control circuit, wherein the control system is configured to wake the CDR circuit for an amount of time based on the timer control circuit in response to a signal from the temperature control circuit.

13. The slave IC of claim 8 , wherein the transmitter further comprises a serializer.

14. The slave IC of claim 8 , wherein the receiver further comprises a deserializer configured to pass a received slave clock signal to the control system.

15. A system comprising:
an interchip bus;
a first integrated circuit (IC) comprising:
a first bus interface configured to be coupled to the interchip bus;
a first transmitter comprising a first driver, the first driver outputting a first data signal to the first bus interface for transmission across the interchip bus;
a first receiver coupled to the first bus interface;
a first clock data recovery (CDR) circuit operatively coupled to the first receiver;
a first control system operatively coupled to the first CDR circuit; and
a temperature control circuit operatively coupled to the first control system and the first CDR circuit, wherein the control system wakes the first CDR circuit based on changes in temperature and the temperature control circuit; and

a second IC comprising:
a second bus interface configured to be coupled to the interchip bus;
a second transmitter comprising a second driver, the second driver outputting a second data signal to the second bus interface for transmission across the interchip bus;
a second receiver coupled to the second bus interface, the second receiver configured to extract a clock signal from a signal received from the first IC through the interchip bus;
a second CDR circuit operatively coupled to the second receiver; and
a second control system operatively coupled to the second receiver and the second CDR circuit, the second control system configured to operate on the clock signal extracted by the second receiver without reference to an internal phase locked loop (PLL) or internal clock; and

a sole active PLL shared between the first IC and the second IC, the sole active PLL configured to provide the clock signal for use by both the first IC and the second IC.

16. The system of claim 15 wherein the first control system and the second control system are configured to negotiate which of the first control system and the second control system will be a master control system and which of the first control system and the second control system will be a slave control system.

17. The system of claim 16 , further comprising an inactive PLL associated with the slave control system, wherein the inactive PLL is configured to remain inactive after the negotiation of which of the first control system and the second control system will be the master control system.

18. The system of claim 16 , wherein the master control system is configured to change frequencies on the interchip bus to reduce electromagnetic interference (EMI).

19. The system of claim 16 , wherein the master control system is configured to change a programmable termination of the first receiver based on a distance between the first IC and the second IC.

Assignees

• Qualcomm Inc

Inventors

• Thurston Jason Alan
• Arcudia Kenneth Luis

Classifications

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• Y02B60/1235

  Cross-Sectional Technologies · mapped topic

• Y02B60/1228

  Cross-Sectional Technologies · mapped topic