Microcontroller for memory management unit

Patent metadata

Field	Value
Publication number	US-9792220-B2
Application number	US-201314011655-A
Country	US
Kind code	B2
Filing date	Aug 27, 2013
Priority date	Mar 15, 2013
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

First claim

What is claimed is:

1. A system configured to perform one or more preparatory operations for a memory access operation, the system comprising:
a first memory that includes a first page table;
a memory management unit coupled to the first memory and included within a parallel processing unit, the memory management unit configured to:
process requests for translating virtual memory addresses to physical memory addresses, and
manage the first page table; and

a microcontroller coupled to the memory management unit and included within the parallel processing unit, the microcontroller configured to:
identify a potential memory operation, and
perform the one or more preparatory operations for the potential memory operation, wherein the one or more preparatory operations comprise updating an opportunistic migration indicator included in a first entry in a second page table to identify a first memory page as a candidate for possible migration to a different physical memory at a later time.

2. The system of claim 1 , wherein the potential memory operation comprises an opportunistic memory migration operation associated with a first virtual memory address.

3. The system of claim 2 , wherein the one or more preparatory operations further comprise:
determining that the first memory page is included in a second memory based on the first virtual memory address, wherein the second memory is associated with a second processing unit;
allocating a storage space in the first memory based on the size of the first memory page; and
writing to a command queue one or more migration commands that are associated with migrating the first memory page from the second memory to the first memory.

4. The system of claim 3 , wherein the system further comprises a copy engine coupled to the first memory and configured to execute memory copy commands included in the command queue.

5. The system of claim 4 , wherein the one or more migration commands include commands that, when executed by the copy engine, cause the copy engine to copy the first memory page from the second memory to the first memory.

6. The system of claim 5 , wherein the one or more migration commands further include commands that, when executed by the parallel processing unit, cause the parallel processing unit to update the first page table to map the first virtual memory address to the first memory.

7. The system of claim 6 , wherein the one or more migration commands further include commands that, when executed by the parallel processing unit, cause the parallel processing unit to update the second page table to remove any mappings corresponding to the first virtual memory address, wherein the second page table is associated with the second memory.

8. The system of claim 1 , wherein identifying the potential memory operation comprises scanning entries included in a page state directory to identify a first entry that is associated with a first virtual memory address and reflects an opportunistic memory migration status.

9. The system of claim 8 , wherein the first entry reflects an opportunistic migration status.

10. The system of claim 9 , wherein the first entry indicates that the first page table maps the first virtual memory address to a memory page included in a second memory.

11. The system of claim 1 , wherein the potential memory operation comprises a zero-fill-on-demand memory operation, and the one or more preparatory operations further comprise allocating a second memory page included in the first memory and setting every entry included in the second memory page to a binary value of zero.

12. The system of claim 1 , wherein the potential memory operation comprises a copy-on-write memory operation, and the one or more preparatory operations further comprise allocating a second memory page included in the first memory and copying a copy-on-write memory page to the second memory page.

13. A computing device, comprising:
a first memory that includes a first page table;
a memory management unit included within a parallel processing unit, the memory management unit configured to:
process requests for translating virtual memory addresses to physical memory addresses, and
manage the first page table; and

a microcontroller included within the parallel processing unit, the microcontroller configured to:
identify a potential memory operation, and
perform one or more preparatory operations for the potential memory operation, wherein the one or more preparatory operations comprise updating an opportunistic migration indicator included in a first entry in a second page table to identify a first memory page as a candidate for possible migration to a different physical memory at a later time.

14. The computing device of claim 13 , wherein the potential memory operation comprises an opportunistic memory operation associated with a first virtual memory address, and the one or more preparatory operations further comprise:
determining that the first memory page is included in a second memory based on the first virtual memory address, wherein the second memory is associated with a second processing unit and includes the second page table;
allocating a storage space in the first memory based on the size of the first memory page; and
writing to a command queue one or more migration commands that are associated with migrating the first memory page from the second memory to the first memory.

15. The computing device of claim 13 , wherein the potential memory operation comprises a zero-fill-on-demand memory operation, and the one or more preparatory operations further comprise allocating a second memory page included in the first memory and setting every entry included in the second memory page to a binary value of zero.

16. The computing device of claim 13 , wherein the potential memory operation comprises a copy-on-write memory operation, and the one or more preparatory operations further comprise allocating a second memory page included in the first memory and copying a copy-on-write memory page to the second memory page.

17. A computer-implemented method for performing one or more preparatory operations for a memory access operation, the method comprising:
identifying a potential memory operation; and
performing the one or more preparatory operations for the potential memory operation, wherein the one or more preparatory operations comprise updating an opportunistic migration indicator included in a first entry in a first page table to identify a first memory page as a candidate for possible migration to a different physical memory at a later time.

18. The method of claim 17 , wherein the potential memory operation comprises an opportunistic memory migration operation associated with a first virtual memory address, and the one or more preparatory operations further comprise:
determining that the first memory page is included in a first memory based on the first virtual memory address, wherein the first memory is associated with a first processing unit, and includes the first page table;
allocating a storage space in a second memory based on the size of the first memory page, wherein the second memory is associated with a second processing unit; and
writing to a command queue one or more migration commands that are associated with migrating the first memory page from the first memory to the second memory.

19. The method of claim 17 , wherein the potential memory operation comprises a zero-fill-on-demand memory operation, and the one or more preparatory operations further comprise allo

Assignees

• Nvidia Corp

Inventors

• Buschardt Cameron
• Duluk Jr Jerome F
• Mashey John
• Hairgrove Mark
• Deming James Leroy
• Fahs Brian

Classifications

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/684

  TLB miss handling · CPC title

• G06F2212/301

  In special purpose processing node, e.g. vector processor · CPC title

• G06F12/10

  Address translation · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title