Memory controller and memory system including the same

Patent metadata

Field	Value
Publication number	US-9792206-B2
Application number	US-201414179661-A
Country	US
Kind code	B2
Filing date	Feb 13, 2014
Priority date	Mar 7, 2013
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

An operating method is for a memory device which controls a nonvolatile memory. The operating method includes managing a program depth bit map indicating an upper page program state of each of a plurality of word lines of the nonvolatile memory in response to an external write request, and outputting one of a plurality of different read commands to the nonvolatile memory based on information of the program depth bit map corresponding to a word line to be accessed in response to an external read request.

First claim

What is claimed is:

1. An operating method of a memory device which controls a nonvolatile memory, the operating method comprising:
managing a program depth bit map indicating an upper page program state of each of a plurality of word lines of the nonvolatile memory in response to an external write request, by a memory controller, where the program depth bit map is stored in a buffer memory in the memory controller which is separate from the nonvolatile memory; and
outputting one of a plurality of different read commands to the nonvolatile memory based on information of the program depth bit map corresponding to a word line to be accessed in response to an external read request,
wherein the plurality of different read commands comprises a first read command directing a read operation on a word line only having a lower page program state, and a second read command directing a read operation on a word line having an upper page program state,
wherein a read time corresponding to a lower page read operation of the nonvolatile memory executed according to the first read command is the same as a read time corresponding to a lower page read operation of the nonvolatile memory executed according to the second read command, and
wherein a read operation of the nonvolatile memory executed according to each of the first and second read commands does not include an operation of determining an upper page program state of the word line to be accessed.

2. The operating method of claim 1 , wherein at least 2-page data is stored at memory cells of each word line.

3. A memory system, comprising:
at least one nonvolatile memory; and
a memory controller configured to control the at least one nonvolatile memory, the memory controller including a buffer memory separate from the nonvolatile memory, the buffer memory being configured to store therein a program depth bit map indicating an upper page program state of each of a plurality of word lines of the at least one nonvolatile memory,
wherein the memory controller is responsive to an external read request to provide the at least one nonvolatile memory with one of a plurality of different read commands based on bit information, corresponding to a word line to be accessed, of the program depth bit map, and
wherein the at least one nonvolatile memory includes flag cells for storing program states of the word lines, and wherein the flag cells are accessed to form the program depth bit map before the at least one nonvolatile memory is provided with the one of the plurality of different read commands.

4. The memory system of claim 3 , wherein the memory controller is responsive to an external write request to manage the program depth bit map in accordance with the external write request.

5. The memory system of claim 4 , wherein the plurality of read commands comprises a first read command directing a read operation on a word line only having a lower page program state, and a second read command directing a read operation on a word line having an upper page program state.

6. The memory system of claim 5 , wherein when the first read command is received, the at least one nonvolatile memory performs a read operation on lower page data of the word line to be accessed.

7. The memory system of claim 6 , wherein when the second read command is received, the at least one nonvolatile memory performs a read operation on one of lower page data and upper page data of the word line to be accessed based on a page address input together with the second read command.

8. The memory system of claim 7 , wherein a read time corresponding to lower page data of the nonvolatile memory executed according to the first read command is the same as a read time corresponding to lower page data of the nonvolatile memory executed according to the second read command.

9. The memory system of claim 3 , wherein the at least one nonvolatile memory does not include flag cells for storing program states of the word lines.

10. The memory system of claim 3 , wherein the at least one nonvolatile memory includes memory cells each storing low page data and upper page data.

11. The memory system of claim 5 , wherein a read operation of the nonvolatile memory executed according to each of the first and second read commands does not include an operation of determining an upper page program state of the word line to be accessed.

12. A memory controller comprising:
a host interface configured to interface with a host device;
a memory interface configured to interface with a nonvolatile memory which includes a plurality of word lines;
a processor configured to transmit commands to the memory interface in accordance with requests received from the host interface; and
a memory configured to store therein a program depth bit map indicating an upper bit program state of each of the plurality of word lines of the nonvolatile memory,
wherein the processor is responsive to a read request received via the host interface to access the memory to determine the upper bit program state of a word line to be accessed among the plurality of word lines, and to transmit one of plural different read commands to the memory interface in accordance with the determined upper bit program state of the word line to be accessed,
wherein the nonvolatile memory includes flag cells for storing program states of the word lines, and
wherein the memory controller is further configured to access the flag cells to form the program depth bit map before transmitting the one of the plural different read commands to the memory interface in accordance with the determined upper bit program state of the word line to be accessed.

13. The memory controller of claim 12 , wherein the processor is configured to update the bit map in response to a write request received via the host interface.

14. The method of claim 1 , wherein the at least one nonvolatile memory includes flag cells for storing program states of the word lines, the method further comprising accessing the flag cells to form the program depth bit map before outputting the one of the plurality of different read commands to the nonvolatile memory based on the information of the program depth bit map.

Assignees

• Kim Moosung
• Jung Dawoon
• Samsung Electronics Co Ltd

Inventors

• Kim Moosung
• Jung Dawoon

Classifications

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/34 Primary

  Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title