Processing device with self-scrubbing logic

US9792184B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9792184-B2
Application numberUS-201614997969-A
CountryUS
Kind codeB2
Filing dateJan 18, 2016
Priority dateFeb 22, 2013
Publication dateOct 17, 2017
Grant dateOct 17, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic. The apparatus also includes an external memory external to the processing unit and coupled to send configuration data to the configuration memory in response to a data feed signal outputted by the self-scrubber logic.

First claim

Opening claim text (preview).

What is claimed is: 1. A processing device including: self-scrubber logic coupled to send a heartbeat signal to a watchdog unit that is external to the processing device, the processing device coupled to be selectively reset by the watchdog unit that is external to the processing device; and configuration memory coupled to be loaded with configuration data from an external memory that is external to the processing device, wherein the self-scrubber logic is coupled to read the configuration memory to detect compromised data stored in the configuration memory and correct the compromised data, and wherein the self-scrubber logic is also coupled to output a data feed signal to the external memory in response to the compromised data including a threshold level of flipped bits, the data feed signal outputted by the self-scrubber logic to facilitate loading the configuration data into the configuration memory. 2. The processing device of claim 1 , wherein, in response to detecting compromised data in the configuration memory, the self-scrubber logic is coupled to facilitate rewriting substantially all of the configuration memory with the configuration data when the compromised data includes the threshold level of flipped bits and coupled to correct a targeted portion of the configuration memory when the compromised data includes less than the threshold level of flipped bits. 3. The processing device of claim 2 , wherein the targeted portion of the configuration memory is a frame, and wherein the self-scrubber logic is coupled to correct the flipped bits based on a golden frame when the frame includes less than the threshold level of flipped bits. 4. The processing device of claim 3 , wherein the golden frame is stored in the external memory. 5. A method comprising: detecting an inconsistency between a frame of configuration data and a golden frame, wherein a processing device includes a configuration memory including the configuration data; and correcting the inconsistency between the frame and the golden frame based on a threshold level of flipped bits in the frame, wherein said correcting the inconsistency includes loading a bitfile from an external memory into the configuration memory when the inconsistency between the frame and the golden frame reaches the threshold level of flipped bits, and wherein said correcting the inconsistency includes correcting the frame of configuration data when the inconsistency between the frame and the golden frame is below the threshold level of flipped bits, said detecting the inconsistency and said correcting the inconsistency initiated by self-scrubber logic disposed within the processing device. 6. The method of claim 5 further comprising; monitoring the self-scrubber logic to detect a failure in the self-scrubber logic; and resetting the processing device in response to detecting the failure of the self-scrubber logic. 7. The method of claim 6 , wherein said monitoring the self-scrubber logic and said resetting the processing device is performed with a watchdog unit external to the processing device. 8. The method of claim 5 , wherein detecting the inconsistency includes utilizing a cyclical redundancy check (“CRC”) that checks substantially all of the configuration memory for CRC errors. 9. The method of claim 5 further comprising: storing an address of the frame within the processing device before said correcting the inconsistency; and storing data content of the frame within the processing device before said correcting the inconsistency. 10. The method of claim 5 , wherein said correcting the frame of the configuration data includes correcting the flipped bits based on a golden frame. 11. A non-transitory machine-accessible storage medium that provides instructions that, when executed by a processing device, will cause the processing device to perform operations comprising: detecting an inconsistency between a frame of configuration data and a golden frame, wherein the processing device includes the configuration data; and correcting the inconsistency between the frame and the golden frame based on a threshold level of flipped bits in the frame, wherein correcting the inconsistency includes loading a bitfile from an external memory into the configuration memory when the inconsistency between the frame and the golden frame reaches the threshold level of flipped bits, and wherein correcting the inconsistency includes correcting the frame of configuration data when the inconsistency between the frame and the golden frame is below the threshold level of flipped bits, said detecting the inconsistency and said correcting the inconsistency performed by self-scrubber logic disposed within the processing device. 12. The non-transitory machine-accessible storage medium of claim 11 , further providing instructions that, when executed by the processing device, will cause the processing device to perform further operations, comprising: monitoring the self-scrubber logic to detect a failure in the self-scrubber logic; and resetting the processing device in response to detecting the failure of the self-scrubber logic. 13. The non-transitory machine-accessible storage medium of claim 11 , wherein said monitoring the self-scrubber logic and said resetting the processing device is performed with a watchdog unit external to the processing device. 14. The non-transitory machine-accessible storage medium of claim 11 , wherein detecting the inconsistency includes utilizing a cyclical redundancy check (“CRC”) that checks substantially all of the configuration memory for CRC errors.

Assignees

Inventors

Classifications

  • in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

  • Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

  • by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

  • in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

  • Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

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What does patent US9792184B2 cover?
An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to t…
Who is the assignee on this patent?
Sandia Corp, Sandia Llc Nat Tech & Eng Solutions
What technology area does this patent fall under?
Primary CPC classification G06F11/0757. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 17 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).