Hardware assisted inter hypervisor partition data transfers

Patent metadata

Field	Value
Publication number	US-9792136-B2
Application number	US-201113096680-A
Country	US
Kind code	B2
Filing date	Apr 28, 2011
Priority date	Apr 28, 2011
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

An invention is disclosed for effectuating direct memory access (DMA) transfers by a guest operating system of a child partition. A guest operating system is presented with virtualized resources rather than physical resources—e.g. a virtualized processor, virtualized memory, and a virtualized DMA controller. When the guest OS attempts to initiate a DMA transfer using the virtualized DMA controller, the child partition detects this, and directs the physical DMA controller to conduct the DMA transfer.

First claim

What is claimed:

1. A method for offloading data transfer operations between a virtualized hardware device and a first child partition among a plurality of child partitions from a central processing unit (CPU) of a host computer having a host partition, the method comprising:
determining, by the first child partition, that a guest system operating on the first child partition has attempted to instruct a virtualized hardware device of the first child partition to copy first data to a first destination allocated to a second child partition of the host computer, wherein the first destination has a physical address allocated to the second child partition;
in response to determining, instructing the CPU, by a virtual machine manager (VMM) that controls access to physical memory by the first child partition and the second child partition, to process a first instruction indicative of instructing a controller or a physical resource having direct access to physical memory to write the first data to the first destination; and
sending a message from the virtual machine manager (VMM) to the first child partition indicative of the status of the data transfer.

2. The method of claim 1 , further comprising:
sending, from the first child partition to the VMM, an indication of instructing the CPU to process the first instruction.

3. The method of claim 2 , wherein sending, from the first child partition to the VMM, the indication of instructing the CPU to process the first instruction comprises:
translating, by the VMM, a location of the first data in a virtual address space of the first child partition to a location of the first data in an address space of the host partition.

4. The method of claim 2 , wherein sending, from the first child partition to the VMM, the indication of instructing the CPU to process the first instruction comprises:
translating, by the VMM, a location of the first data in an address space of the host partition to a location of the first data in a physical address space.

5. The method of claim 2 , wherein sending, from the first child partition to the VMM, the indication of instructing the CPU to process the first instruction comprises:
sending the first instruction, by the first child partition and to the VMM, across a shared memory transport.

6. The method of claim 1 , further comprising:
sending an indication, by the physical hardware device and to the CPU, that the first data has been written to the first destination;
sending an indication, by the CPU and to the first child partition, that the first data has been written to the first destination;
writing, by the first child partition, second data to a location of the first data in an address space of the first child partition, the second data overwriting at least a portion of the first data;
determining, by the first child partition, that the guest system has attempted to instruct the virtualized hardware device of the first child partition to write the second data to a second destination;
instructing the CPU, by the first child partition, to process an instruction originated by the first child partition indicative of instructing the physical hardware device to write the second data to the second destination; and
causing the CPU to instruct the physical hardware device to write the first data to the first destination.

7. The method of claim 1 , further comprising:
instructing, by the CPU, a direct memory access (DMA) controller of the host computer to write the first data to the first destination; and
writing, by the DMA controller, the first data to the first destination, the first destination being part of the physical hardware device.

8. The method of claim 1 , further comprising:
determining, by a second child partition of the host computer, that a second guest system of the second child partition has attempted to instruct a second virtualized hardware device of the second child partition to write second data to a second destination, the second virtualized hardware device corresponding to the physical hardware device;
instructing the CPU, by the VMM, to process an instruction indicative of instructing the physical hardware device to write the second data to the second destination; and
causing the CPU to instruct the physical hardware device to write the second data to the second destination.

9. A system for offloading data transfer operations between a virtualized hardware device and a first child partition among a plurality of child partitions, the system comprising:
a processor; and a memory communicatively coupled to the processor when the system is operational, the memory bearing processor-executable instructions that, upon execution by the processor, cause the system at least to:
determine, by the first child partition, that a guest system operating on the first child partition has attempted to instruct a virtualized hardware device of the first child partition to write first data to a first destination allocated to a second child partition of the system, wherein the first destination has a physical address allocated to the second child partition;
in response to determining, instruct a CPU, by a virtual machine manager (VMM) that controls access to physical memory by the first child partition and the second child partition, to process an instruction indicative of instructing a controller or a physical resource having direct access to physical memory to write the first data to the first destination to instruct the controller or the physical resource having direct access to physical memory to write the first data to the first destination; and
sending a message from the virtual machine manager (VMM) to the first child partition indicative of the status of the data transfer.

10. The system of claim 9 , wherein the processor-executable instructions that, upon execution by the processor, cause the system at least to instruct the CPU to process the instruction further cause the system at least to:
send, from the first child partition and to the VMM, an indication of instructing the CPU to process the instruction.

11. The system of claim 10 , wherein the memory further bears processor-executable instructions that, upon execution by the processor, further cause the system at least to:
translate, by the VMM, a location of the first data in a virtual address space of the first child partition to a location of the first data in an address space of the host partition.

12. The system of claim 10 , wherein the memory further bears processor-executable instructions that, upon execution by the processor, cause the system at least to:
translate, by the VMM, a location of the first data in an address space of the host partition to a location of the first data in a physical address space.

13. The system of claim 10 , wherein the memory further bears processor-executable instructions that, upon execution by the processor, cause the system at least to:
send the instruction, by the first child partition and to the VMM, across a shared memory transport.

14. The system of claim 9 , wherein the memory further bears processor-executable instructions that, upon execution by the processor, further cause the system at least to:
send an indication, by the physical hardware device and to the CPU, that the first data has been written to the first destination;
send an indication, by the CPU and to the first child partition, that the first data has been written to the first destination;
write, by the first child partition, second data to a location of the first data in an address space of the first child partition, the second data overwriting at least a portion

Assignees

• Pavlov Vladimir
• Microsoft Technology Licensing Llc

Inventors

• Pavlov Vladimir

Classifications

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title