Method of aligning quadrate wafer in first photolithography process

Patent metadata

Field	Value
Publication number	US-9791790-B2
Application number	US-201414901541-A
Country	US
Kind code	B2
Filing date	Jan 3, 2014
Priority date	Oct 16, 2013
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.

First claim

The invention claimed is:

1. A method of aligning a quadrate wafer in a first photolithography process comprising:
fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask;
during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and
performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process;
wherein the mask aligning markers include bars that are parallel to sides of the quadrate wafer respectively.

2. The method according to claim 1 , wherein the aligning markers include at least two pairs of bars.

3. The method according to claim 2 , wherein each pair of bars are configured as a right-angle shaped aligning marker or a crisscross aligning marker.

4. The method according to claim 3 , wherein inner sides of at least two right-angle shaped aligning markers or at least two crisscross aligning markers are parallel to sides at at least two corners of the quadrate wafer respectively.

5. The method according to claim 2 , wherein four bars of two pairs of bars are connected to form a quadrate -frame, or are separated from one another.

6. The method according to claim 3 , wherein the aligning markers includes two, three or four right-angle shaped aligning markers or crisscross aligning markers.

7. The method according to claim 3 , wherein the aligning markers include two right-angle shaped aligning markers each comprising a pair of bars, the bars of each of the two right-angle shaped aligning markers being respectively aligned with sides of a corresponding one of two opposite corners of the quadrate wafer.

8. The method according to claim 1 , wherein the aligning markers are configured as a quadrate-frame aligning marker;
inner sides of the quadrate -frame aligning marker are parallel to peripheral edges of the quadrate wafer respectively.

9. The method according to claim 2 , wherein inner sides of the aligning markers are spaced from respective edges of the quadrate wafer by a distance d in a range from 0 μm to 50 μm.

10. The method according to claim 1 , wherein the quadrate wafer is made of GaN, Si, SiC, GaAs, AlGaInP or GaP.

11. The method according to claim 1 , wherein the method is implemented when producing a LED, a laser, a photoelectric detector or a solar cell device.

Assignees

• Inst Semiconductors Cas

Inventors

• Li Jinmin
• Wang Junxi
• Kong Qingfeng
• Guo Jinxia
• Yi Xiaoyan

Classifications

• G03F9/7084 Primary

  Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels · CPC title

• G03F1/42

  Alignment or registration features, e.g. alignment marks on the mask substrates · CPC title