Array substrate, manufacture method thereof, and display device

Patent metadata

Field	Value
Publication number	US-9791733-B2
Application number	US-201615204318-A
Country	US
Kind code	B2
Filing date	Jul 7, 2016
Priority date	Dec 29, 2014
Publication date	Oct 17, 2017
Grant date	Oct 17, 2017

Abstract

An array substrate, a display device and a method for fabrication the array substrate are provided. The array substrate comprises a base substrate; gate lines and data lines; pixel electrodes; a common electrode layer including at least one first slot and at least one second slot at least partially overlapped with the first slot; at least one shielding electrode disposed above the data line; and at least one shielding branch electrode disposed above the gate line and electrically connected to the shielding electrode. A projection of the shielding electrode onto the data line is at least partially overlapped with the data line, a projection of the shielding branch electrode onto the gate line is at least partially overlapped with the gate line, and the array substrate exhibits at least one raised area where the at least one shielding branch electrode is embedded.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a plurality of gate lines and a plurality of data lines disposed on the base substrate, wherein the plurality of gate lines and the plurality of data lines are insulated from each other and cross each other to define a plurality of pixel units;
a plurality of pixel electrodes;
a common electrode layer including at least one first slot and at least one second slot, wherein the at least one second slot is at least partially overlapped with the at least one first slot, and the common electrode layer has a plurality of common electrodes;
at least one shielding electrode disposed above a data line; and
at least one shielding branch electrode disposed above a gate line and electrically connected to the at least one shielding electrode,
wherein the at least one first slot and the at least one shielding electrode are extending in an extension direction of the plurality of data lines, the at least one second slot and the at least one shielding branch electrode are extending in an extension direction of the plurality of gate lines, a projection of the at least one shielding electrode onto the data line is at least partially overlapped with the data line, a projection of the at least one shielding branch electrode onto the gate line is at least partially overlapped with the gate line, and the array substrate exhibits at least one raised area where the at least one shielding branch electrode is embedded.

2. The array substrate according to claim 1 , wherein:
along a direction perpendicular to the array substrate, a projection of the at least one first slot on the array substrate is at least partially overlapped with at least one of a projection of a pixel electrode on the array substrate and a projection of the data line on the array substrate.

3. The array substrate according to claim 1 , wherein:
along a direction perpendicular to the array substrate, a pixel electrode is disposed between the at least one shielding branch electrode and the data line; and
the at least one shielding branch electrode is disposed between the common electrode layer and the pixel electrode.

4. The array substrate according to claim 3 , wherein:
a seventh insulating layer having at least one fourth via hole is disposed between the at least one shielding branch electrode and the common electrode layer; and
a common electrode is electrically connected to the at least one shielding branch electrode or the at least one shielding electrode through the at least one fourth via hole.

5. The array substrate according to claim 4 , wherein:
the seventh insulating layer exhibits at least one raised area where the at least one shielding branch electrode is embedded.

6. The array substrate according to claim 1 , wherein:
along a direction perpendicular to the array substrate, the common electrode layer is disposed between the at least one shielding branch electrode and the data line; and
the at least one shielding branch electrode is disposed between the common electrode layer and a pixel electrode.

7. The array substrate according to claim 6 , wherein:
a sixth insulating layer having at least one fifth via hole is disposed between the at least one shielding branch electrode and the common electrode layer; and
a common electrode is electrically connected to the at least one shielding branch electrode or the at least one shielding electrode through the at least one fifth via hole.

8. The array substrate according to claim 7 , wherein:
a seventh insulating layer is disposed between the at least one shielding branch electrode and the pixel electrode; and
the seventh insulating layer exhibits at least one raised area where the at least one shielding branch electrode is embedded.

9. A display device, comprising:
an array substrate comprising:
a base substrate;
a plurality of gate lines and a plurality of data lines disposed on the base substrate, wherein the plurality of gate lines and the plurality of data lines are insulated from each other and cross each other to define a plurality of pixel units;
a plurality of pixel electrodes;
a common electrode layer including at least one first slot and at least one second slot, wherein the at least one second slot is at least partially overlapped with the at least one first slot, and the common electrode layer has a plurality of common electrodes;
at least one shielding electrode disposed above a data line; and
at least one shielding branch electrode disposed above a gate line and electrically connected to the at least one shielding electrode,
wherein the at least one first slot and the at least one shielding electrode are extending in an extension direction of the plurality of data lines, the at least one second slot and the at least one shielding branch electrode are extending in an extension direction of the plurality of gate lines, a projection of the at least one shielding electrode onto the data line is at least partially overlapped with the data line, a projection of the at least one shielding branch electrode onto the gate line is at least partially overlapped with the gate line, and the array substrate exhibits at least one raised area where the at least one shielding branch electrode is embedded;

an opposite substrate including a plurality of photo spacers; and
display medium sandwiched between the array substrate and the opposite substrate,
wherein at least one photo spacer is attached to the at least one raised area where the at least one shielding branch electrode is embedded.

10. The display device according to claim 9 , wherein:
along a direction perpendicular to the array substrate, a projection of the at least one first slot on the array substrate is at least partially overlapped with at least one of a projection of a pixel electrode on the array substrate and a projection of the data line on the array substrate.

11. The display device according to claim 9 , wherein:
along a direction perpendicular to the array substrate, a pixel electrode is disposed between the at least one shielding branch electrode and the data line; and
the at least one shielding branch electrode is disposed between the common electrode layer and the pixel electrode.

12. The display device according to claim 9 , wherein:
along a direction perpendicular to the array substrate, the common electrode layer is disposed between the at least one shielding branch electrode and the data line; and
the at least one shielding branch electrode is disposed between the common electrode layer and a pixel electrode.

13. A method for fabricating an array substrate, comprising:
providing a base substrate,
forming a plurality of gate lines on the base substrate;
forming a plurality of data lines on the base substrate, wherein the plurality of gate lines and the plurality of data lines are insulated from each other and cross each other to define a plurality of pixel units,
forming a fifth insulating layer on the plurality of data lines;
forming a plurality of pixel electrodes above the plurality of data lines;
forming at least one shielding electrode above a data line and at least one shielding branch electrode above a gate line, wherein the at least one shielding electrode and the at least one shielding branch electrode are electrically connected;
forming a common electrode layer including at least one first slot and at least one second slot above the plurality of data lines, wherein the at least one first slot is at least partially overlapped with the at least one second slot and the common electrode layer includes a plurality of common electrodes,
wherein the a

Assignees

• Shanghai Tianma Microelectronics Co Ltd
• Tianma Microelectronics Co Ltd

Inventors

• Ding Hong
• Yao Qijun
• Du Lingxiao
• Ma Jun
• Li Xiaoye

Classifications

• G02F2201/121

  common or background · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/13394

  spacers regularly patterned on the cell subtrate, e.g. walls, pillars (G02F1/133377 takes precedence) · CPC title

• H01L27/1244

  Electricity · mapped topic